Published:2011/8/3 3:40:00 Author:Li xiao na From:SeekIC
By Paul Goossens
Structure
Verilog source code is always organized using the same structure. It starts with the module declaration. This part of the code begins with the word ’module’. followed by a name, This is accompanied by a collection of inputs and outputs in brackets, separated by commas. The whole thing is terminated by a semicolon. This can be seen in lines 30-35 of our example.
The next thing you have to do is to define the directions of the signals (ports) identified in the module declaration. You can see how this is done in lines 39-45 of our example. There are three options for each signal: input, output, or input (bi-directional). Here we have only used ’input’ and ’output’. Each line is terminated by a semicolon (;). In the first line, you can see that several signals can be defined in a single line if commas are used to separate the definitions.
The outputs require an additional specification. If the function of an output is described in a procedural statement (don’t worry, we’ll explain what this means further on), it must have the type reg (register = output of a flip-flop). In line 47, signals D2, D3 and D4 are defined as registers.
Now that we’ve taken care of the administrative duties, we can start with the actual design. This example, as befits every initial example, is very simple. Here we demonstrate the ways in which signals can be described using Boolean algebra.
This can be done in two mariners in Verilog: either by using an assign statement, or in what is called a ’procedural statement’. Listing 1 shows an example of each of these methods. The first method is demonstrated in line 50. Here the description says that signal Dl is the result of an AND operation on signals S1-S4. That’s another way of saying that Dl is only active if S1-S4 are also active (’1’). In all other cases, Dl is inactive (’0’).
The symbol ’&’ thus stands for the AND function. The Boolean functions in Verilog are summarized in Table 1.
Procedural statements
The remaining outputs (D2-D4) are described in a procedural statement. Procedural statements are always preceded by the word a/ways. This keyword is described in more detail in one of our later examples.
Just as in the Pascal programming language, you can combine a group of statements into a unit by using the keywords begin and end. All of the statements between these two words are collectively regarded as being a single statement.
If you look at line 54, you will see that signal D4 is described as a signal that becomes active if SI or S2 or S3 or S4 is active. Here we intentionally used the word "becomes’ instead of ’is’. The symbol <= means ’becomes’ or ’assumes the value’. As a general rule, we can say that this symbol is used in a procedural statement instead of the = sign.
It’s not difficult to figure out the functions of signals D3 and D4 if you use Table 1 for a bit of help.
The advantage of putting signals in procedural statements instead of working with assign statements will become clear in a later example. Finally, the keyword endmodule indicates that the description of the module is finished.
Compiling
Now we’re getting close to the point where you have to roll up your sleeves and get to work. First, the design has to be compiled. The compiler already knows exactly which signal must be connected to each pin of the CPLD. That’s because we already did this for you. This makes compiling child’s play; just click on Start Compilation in the Processing menu and the software go into action.
Various messages will be shown on the screen, and several progress bars will move along. After a while, the program will report that the compilation was successful. That means it has created a programming file that you can use to program your IC.
Reprinted Url Of This Article: http://www.seekic.com/blog/project_solutions/2011/08/03/Design_Your_Own_IC__Part_2__CPLDs_in_practice_(2).html
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