Published:2011/8/4 0:45:00 Author:Li xiao na From:SeekIC
By Paul Goossens
Always @
Up to line 46, there’s nothing new to be seen. But in line 46 you can see something added to the keyword always: an @ character followed by a comparison. This code segment can also be seen in Listing 2. The @ sign indicates that the procedural statements belonging to this always statement are only allowed to be evaluated (but not ’executed’; only processors execute statements) if the following comparison is satisfied In this case, that means that the following statements are only applicable at the moment when the clock signal (CLK) OR the reset signal OR the SET signal has a rising edge (posedge). Just to avoid any confusion, a rising edge is the transition from a Low level to a High level.
Verilog also has the modifier ’negedge’, which in normal English means ’negative edge’ or ’falling edge’.
If any one of these conditions is satisfied, this section of the code is evaluated. First, a check is made to see whether the RESET signal is T. If this is the case, OUT becomes inactive (’0’) and this code segment is done. Otherwise, a check is made to see whether the SET signal is ’1’. If it is, the OUT output goes to T and the code is done. Beside the values ’1’ and ’0’, each signal can also assume the values ’x’ (unknown) or ’z’ (high impedance).
If neither RESET nor SET is T, CLK must have a rising flank, since otherwise this code would not have been evaluated. The intention is that on the rising edge of the clock signal, the output of the flip-flop assumes the value present at the input.
But what happens to the output whenever there isn’t a rising edge on CLK, RESET or SET? The answer is very simple: nothing. In line 45, the OUT signal is defined to be a register, which means that the value most recently assigned to this signal must be held. Whenever the code is not active, the value of this register will not change. By adding the ’©’ character to the always statement, we can thus indicate the conditions under which a portion of the code is allowed to be evaluated. During the rest of the time, the output that is controlled by this block must remain the same.
From the code, it can clearly be seen that the RESET input has higher priority than the SET input. However, that doesn’t mean that he CPLD evaluates these two signals one after the other when it is operating. The CPLD will respond just as fast to the RESET signal as to the SET signal. The sequence is only important for the compiler. It evaluates a section of code and determines what must happen to the output for every imaginable combination of input signals. Based on this evaluation, the compiler ’designs’ a bit of digital logic that respond in exactly the manner described in the code.
Variations on a theme
A second flip-flop (appropriately named ’flipflop2’) is also shown in the schematic diagram (ex2±df). The associated Verilog file is very similar to the file for the first flip-flop. The only difference with respect to the first flip-flop is that the state of the SET signal is checked before the state of the RESET signal. That means that for this flip-flop, the SET input has a higher priority than the RESET input. The output will thus go to T if the RESET and SET inputs both have a value of "l*. With the first flip-flop, the output will go to ’0’ in this situation.
Reprinted Url Of This Article: http://www.seekic.com/blog/project_solutions/2011/08/04/Design_Your_Own_IC__Part_2__CPLDs_in_practice_(4).html
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