Published:2011/8/4 1:14:00 Author:Li xiao na From:SeekIC
By Paul Goossens
Latch
The final block in the schematic is a latch. A latch is also a frequently used type of component in digital designs. The operation of a latch is actually quite simple. As long as the clock input is T, the latch’s output must be the same as its input. If the input state changes, the output must immediately follow the change. By contrast, if the clock signal is inactive (’0’), the last known state of the output must be retained, regardless of any changes to the input state.
The Verilog file latch example.v shows how this can be described in the Verilog language. The output signal can change if the state of the clock signal changes OR the state of the data input changes. This can happen on the rising edge as well as on the falling edge. After the @ sign you can see ’(posedge CLK or D)’. What’s special about this is that signal D is named without ’posedge’ in front. This means that the code must be evaluated for every change in the state of signal D.
In the code belonging to this a/ways statement, you can see that the compiler first looks at the state of the clock signal. If the clock signal is active (T), the output is the same as the input. Otherwise nothing happens, and the current state of the output remains unchanged.
You can compile this example and program it into the CPLD in exactly the same manner as for the previous example. After doing so, use the experimenter’s board to verify that the design actually does what you expect it to do. After this, as an exercise you can see whether you can provide the latch with SET and RESET inputs. As the saying goes, practice makes perfect!
Arithmetic
The previous examples demonstrate how to describe functions without having to worry about logic gates, Boolean algebra and so on. After working with Verilog with a while, every designer will certainly be able to appreciate this. The relatively trivial tasks are handled by the compiler instead of the designer. Our third example shows that arithmetic is also not difficult in Verilog. In this example we use counters. Counters need clock signals, and that’s where we start.
Figure 1 shows the schematic diagram of a standard crystal oscillator. Except for the inverter, all of the components are present on the experimenter’s board. If we now place an inverter between pins 71 and 81 of the CPLD, we have a crystal oscillator.
If you open Example 3, you will see this inverter drawn between two leads of the IC at the top of the schematic. After the CPLD has been programmed, the result is thus an oscillator whose output (pin 81 on the circuit board) is connected to pin 83 of the CPLD. This input is specially intended to act as a clock input.
Arrays
We assume that you are familiar with doing arithmetic in the binary number system. If you are, you are certainly aware that numbers are usually represented by a group of signals. In Verilog, several signals can be conveniently grouped into a structure called an ’array’.
In the Verilog file for the Count block, you will thus see the following in line 40: output |7:0) D;’. This specifies an array of eight signals (D[7]...D[0)). This group of signals can be collectively written as ’D’.
To avoid possible confusion, we have to explain line 47. Here a new signal is declared. This signal is not present in the module declaration, which means that it is not externally visible (outside the module). Such a signal is purely for internal use.
The next interesting line is line 51: temp=temp+l;’. This shows that we can count by simply using the + sign. Table 2 lists additional arithmetic operators that can be used with arrays in Verilog.
In line 52 you can see a comparison (’= =’ means to check whether the left-hand term is equal to the right-hand term). All of the relational operators (such as ’= =’) are listed in Table 3. The number 24d4000000 may appear a bit strange at first glance. This is the notation for writing numbers in Verilog. The first number indicates how many signals are involved (in this case, 24). The ’d’ indicates that the constant is stated in decimal notation. Finally, ’4000000’ is the actual constant.
In this case we must use 24 signals, since the register temp consists of 24 signals. Note that in Verilog, 24 zeros is not the same as 23 zeros! That means that you must make sure that the same number of signals are present on each side of the ’= =’ symbol.
Reprinted Url Of This Article: http://www.seekic.com/blog/project_solutions/2011/08/04/Design_Your_Own_IC__Part_2__CPLDs_in_practice_(5).html
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