Design Your Own IC--Part 2: CPLDs in practice （6）

Published:2011/8/4 1:29:00 Author:Li xiao na From:SeekIC

By Paul Goossens

Counter

If you analyse the Verilog code, you will see that the value of register temp is incremented on each clock pulse. As soon as the register reaches the value 4,000,000, register D is incremented by the value ’1’, temp becomes ’0’ and output SLOW becomes ’1’. If register temp has not yet reached the value 4,000,000, SLOW receives the value ’0’. With a 4.000-MHz clock signal, this means that the value of register D is incremented once per second, with output SLOW briefly going to ’1’. SLOW is thus a 1-Hz clock signal.

BCD counter

The 1-Hz clock signal goes to the clock input of a BCD counter. This is labelled ’BCD_counter’ in the schematic diagram.

The Verilog code for the BCD counter has three separate sections, each of which begins with an always statement. In addition, we should point out that two registers are declared for internal use: SEG and COUNT.

The first function (starting at line 52) is a counter that causes the COUNT register to count from 0 to 9. When it reaches the value 10. COUNT is reloaded with the value 0.

The second function is traversed each time COUNT changes. In line 60 you will find a new statement with the name case. An example of this can be found in Listing 3. C programmers will find this a familiar concept. In this instance, the case statement has one argument (COUNT). This means that the following lines:
“4’d0: SEG=7bllllll0,
4’dl: SEG=7b0110000;"

can be translated as:

if (COUNT= =4’d0) SEG=7b...
else if (COUNT = =4’d0 SEG=..."

and so on.

The line starting with default is processed if the current value of COUNT does not appear in the list. The last section of the Verilog code starts at line 75. As you can see, it is evaluated if the value of register SEG changes.

An interesting feature of Verilog can be seen in line 76: several signals can be grouped into an array by using the ’{’ and ’}’ characters. As SEG is an array and the outputs for the seven-segment display have been declared as individual signals, they must be combined into an array.

Another possible solution would be to couple each signal to an element of the array, for example by using:

“=SEGA = SEGJ6J;’

This method works just as well, but it would make the code quite a bit longer and thus more difficult to read.

Testing

With regard to testing this example, we must mention a shortcoming of the experimenter’s board.

When the CPLD is being programmed, all of its outputs assume the non-active state. Immediately after being programmed, the CPLD is active. As a result, the oscillator does not start properly. This means that after programming the CPLD, you have to briefly reset it. You can do this by fitting a pushbutton switch with a make contact between pins 2 and 20 of connector K6. Alternatively, you can briefly switch the power off and then on again.

Conclusion

You can do a lot more with the Verilog language than what we’ve been able to describe in this article. Here we have limited ourselves to the most commonly used features of Verilog. Still, these features allow users to design quite complex digital functions. Various sites dealing with a wide variety of designs using Verilog can be found on the Internet. By studying and simulating these designs, you can quickly accumulate experience with this interesting language.

An important aspect that we were unable to discuss in this article (due to lack of space) is simulating designs in Quartus. The Quartus tutorial should help you quite a bit in this regard, and there is also always the Help function. Incidentally, it’s a good idea to develop a design in small parts and simulate these small ’subdesigns’ one by one in order to determine whether they work the way they should.

We would appreciate hearing from readers who have created their own interesting applications using the experimenter’s board. Good luck!

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