Appendix: PSU Regulation Tester

Published:2011/8/10 1:20:00 Author:Li xiao na From:SeekIC

The measurement method for the ’load regulation’ is illustrated in Figure 1. The power supply under test is adjusted to one third of the maximum output voltage. This setting guarantees that the power supply and its variable load are used within their normal operating areas. The load consists of a static part to which, under pulse control, an identical load is connected in parallel. The switching frequency is set at 300 Hz, a value obtained from experimentation. Although most supplies will be able to cope with the 300-Hz variable load, the frequency is high enough to give them a rough time. After all, such a load will typically cause an output signal that will closely resemble the one indicated in Figure 2. This image was produced using an AG coupled oscilloscope — hence you will see the ’alternating voltage’ component resulting from the second load being switched on and off under pulse control. We first come across a peak as a result of the load being switched off (Vp). This peak is damped within a lime tp. Next, the voltage can be seen to sag a little when the load is switched on and rises gradually. However, until the load is switched off again, the output voltage does not return to the original value. The remaining difference is called Vs.



The screenshot shown in Figure 2 only serves to explain the measured parameters. Fortunately, in practice the ratios are different and tp will be much shorter resulting in a smaller surface area under the peak(s). And that’s good news because the surface area determines the energy contained in the peak. The smaller the surface area, the better because this energy can damage, or in any case harm, the load connected to the PSU. This is crucial with, for example, digital circuitry; an integrated circuit operating at 3.3 V may not be powered at a much higher voltage for a considerable period.

Here, the ubiquitous BUZ11 is used but any reasonably compatible type will do just as well. We drove the FET gate with a positive voltage between 0 and 10 V by connecting a 300-Hz square-wave generator adjusted to an output level of 5 Vpp with a DC-offset of 2.5 V. Zener diode Dl protects the FET against a too high output voltage (accidentally) set on the PSU under examination.

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