I²C and SMBus

Published:2011/8/11 1:36:00 Author:Amy From:SeekIC

Paul Goossens

The l2C-bus has been dealt with before in Elektor Electronics. Most readers will know that this bus requires only two sig­nals to communicate between, for exam­ple, a controller and one or more ICs in a circuit. We may also assume that it is well known that this bus was developed by Philips and is used mainly in televi­sions, video recorders, tuners, etc.

Unfortunately, the l2C-bus lacks a number of features that manufacturers of computer motherboards require. They therefore developed their own bus, which has been derived from the l2C-bus. This bus goes by the name SMBus (System Manage­ment Bus). The main task for the protocol is to provide communications between the processor and various temperature sen­sors, battery management/charging-chips and even memory modules, etc. in a PC. Because the SMBus has been derived from the l2C-bus, there are obviously a number of similarities. It is in many cases even possible to let components with an l2C-bus communicate with those with an SMBus and vice versa.

The similarities

Both bus protocols make use of the same start and stop mechanism. A start-condition can be recognized by the falling edge on the data line while the clock line remains high. With a stop-condition, a ris­ing edge appears on the data line while the clock line is high. These two condi­tions are the only situations where the data line may change level when the clock line is high. This can be seen in Figure 1.



Following the start condition there is the 7-bit address that has to be unique for each device connected to the bus. Another similarity is that the bus has a sin­gle pull-up resistor for each signal and the connected chips drive these signal lines with an open-source output, as can be seen in Figure 2. This forms a so-called wired-OR configuration. As soon as one of the chips pulls a signal line to ground, the signal will have a low level, irrespec­tive of what the other chips try to do.

The differences

Naturally there are also a number of dif­ferences between the two protocols. We start with the clock speed. With l2C-bus this can vary from 0 to 100 kHz in NOR­MAL mode and up to 400 kHz in FAST mode. With the SMBus, the clock speed has to be between 10 kHz and 100 kHz. The minimum speed is the result of an additional provision of the SMBus. If the clock line is low for more than 35 ms a time-out situation occurs. All chips on the bus have to detect this time-out and ignore all communications until a valid start-condition occurs. This prevents one chip from disabling the entire communication of the bus.

Another difference is the specified levels for logic high and logic low. In the l2C-specifications a low level is defined as 1.5 V, while with the SMBus a level less than 0.8 V is required. The high-level is different as well: with l2C this has to be a minimum of 3 V, while with the SMBus a level of 2.1V or higher is considered a high level.

This difference in the required voltage lev­els would indicate that both protocols can­not be used with each other. In practice this is not so much of a problem, since most chips will generate signals that range from about zero to nearly the power supply voltage.

The outputs of an SMBus IC are specified to be able to sink at least 100 uA, while l2C requires a minimum sink current of 3 mA. All this is related to the fact that the SMBus is also used in laptops and there­fore have to be a little thrifty with power consumption. This means a higher pull-up resistor is required. A value of 10 kf2 is usually a good starting value so that both SMBus-ICs and l2GICs can communicate together on the same bus.

There are also a number of subtle differ­ences, such as maximum bus capaci­tance, rise- and fall-times, etc, but nothing that will prevent you from connecting an l2C chip to the SMBus or the other way around.

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