21010

Barrier Terminal Blocks BARRIER TERMNAL STRP

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21010 Picture
SeekIC No. : 002363022 Detail

21010: Barrier Terminal Blocks BARRIER TERMNAL STRP

floor Price/Ceiling Price

Part Number:
21010
Mfg:
Molex
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/4/28

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Product Details

Quick Details

Product : Barrier Terminal Blocks Type : Wire to Board
Pitch : 14.3 mm Wire Gauge Range : 18-10
Mounting Style : Through Hole Termination Style : Solder    

Description

Number of Positions / Contacts :
Current Rating :
Voltage Rating :
Mounting Angle :
Contact Plating :
Product : Barrier Terminal Blocks
Mounting Style : Through Hole
Termination Style : Solder
Type : Wire to Board
Wire Gauge Range : 18-10
Pitch : 14.3 mm


Features:






Specifications






Description

The 21010 is a CMOS high speed 1,048,576 X 1 dynamic RAM optimized for high performance applications such as mainframes,graphics and microprocessor systems.The 21010 features fast page mode operation which allows high random access of memory cells within the same row.Features of it are:(1)fast page mode operation;(2)single 5V+/-10% power supply;(3)512 cycles/8 ms refresh;(4)common I/O using "early write";(5)available in plastic DIP(P) and SOJ(T) packages.

The absolute maximum ratings of the 21010 can be summarized as:(1)voltage on any pin relative to Vss:-1V to +7.0V;(2)voltage on power supply relative to Vss:-1V to +7.0V;(3)storage temperature is -55 to +125;(4)power dissipation:600 mW;(5)short circuit output current:50 mA.And the recommended operating conditions are:(1)supply voltage:4.5 to 5.5 V;(2)ground:0 V;(3)input high voltage:2.4 to Vcc+1 V;(4)input low voltage:-1.0 to 0.8 V.

The 21010 contains 1,048,576 memory locations.Twenty address bits are required to address a particular memory location.since the 21010 has only 10 address input pins,time multiplexed addressing is uses to input 10 row and 10 column addresses.The multiplexing is controlled by the timing relationship between the row address strobe,the column address strobe and the valid row and column address inputs.






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