21152

Features: The 21152 has the following features:• Complies fully with Revision 2.1 of the PCI Local Bus Specification,• Complies fully with Revision 1.1 of the PCI-to-PCI Bridge Architecture Specification,• Complies fully with the Advanced Configuration Power Interface (ACPI) Spec...

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SeekIC No. : 004215367 Detail

21152: Features: The 21152 has the following features:• Complies fully with Revision 2.1 of the PCI Local Bus Specification,• Complies fully with Revision 1.1 of the PCI-to-PCI Bridge Architect...

floor Price/Ceiling Price

Part Number:
21152
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2020/4/3

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Product Details

Description



Features:

The 21152 has the following features:
• Complies fully with Revision 2.1 of the PCI Local Bus Specification,
• Complies fully with Revision 1.1 of the PCI-to-PCI Bridge Architecture Specification,
• Complies fully with the Advanced Configuration Power Interface (ACPI) Specification
• Complies fully with the PCI Power Management Specification, Revision 1.01
• Implements delayed transactions for all PCI configuration, I/O, and memory read commands-up to three transactions simultaneously in each direction
• Allows 88 bytes of buffering (data and address) for posted memory write commands in each direction-up to three transactions simultaneously in each direction
• Allows 72 bytes of read data buffering in each direction
• Provides concurrent primary and secondary bus operation to isolate traffic
• Provides five secondary clock outputs
   - Low skew, permitting direct drive of option slots
   - Individual clock control through configuration space
• Provides arbitration support for four secondary bus devices
   - A programmable 2-level arbiter
   - Hardware disable control, permitting use of an external arbiter
• Provides enhanced address decoding
   - A 32-bit I/O address range
   - A 32-bit memory-mapped I/O address range
   - A 64-bit prefetchable memory address range
   - ISA-aware mode for legacy support in the first 64 KB of I/O address range
   - VGA addressing and VGA palette snooping support
• Supports PCI transaction forwarding for the following commands
   - All I/O and memory commands
   - Type 1 to Type 1 configuration commands
   - Type 1 to Type 0 configuration commands (downstream only)
   - All Type 1 to special cycle configuration commands
• Includes downstream lock support
• Supports both 5 V and 3.3 V signaling environments

The 21152 makes it possible to extend a system's load capability limit beyond that of a single PCI bus by allowing motherboard designers to add more PCI devices, or more PCI option card slots, than a single PCI bus can support. Figure 1-1 illustrates the use of two 21152 PCI-to-PCI bridges on a system board. Each 21152 that is added to the board creates a new PCI bus that provides support for the additional PCI slots or devices.



Pinout

  Connection Diagram


Specifications

The 21152 is specified to operate at a maximum frequency of 33 MHz at a junction temperature (Tj) not to exceed 125°C. Table 15-1 lists the absolute maximum ratings for the 21152. Stressing the device beyond the absolute maximum ratings may cause permanent damage. These are stress ratings only. Operating beyond the functional operating range is not recommended, and extended exposure beyond the functional operating range may affect the reliability.
Parameter Minimum Maximum
Tj - 125
Supply voltage, Vcc - 3.9 V
Maximum voltage applied to signal pins - 5.5 V
Maximum power, PWC - 1.2 W @ 33 MHz
Storage temperature range, Tstg -55 125



Description

The 21152 is a second-generation PCI-to-PCI bridge and is fully compliant with PCI Local Bus Specification, Revision 2.1. The 21152 is pin-to-pin compatible with the 21052, which is fully compliant with PCI Local Bus Specification, Revision 2.0.The 21152 provides full support for delayed transactions, enabling buffering of memory read, I/O, and configuration transactions. The 21152 has separate posted write, read data, and delayed transaction queues with significantly more buffering capability than first-generation bridges. In addition, the 21152 supports bi-directional buffering of simultaneous multiple posted write and delayed transactions.Among the features provided by the 21152 are a programmable 2-level secondary bus arbiter, individual secondary clock software control, and enhanced address decoding. The 21152 has sufficient clock and arbitration pins to support four PCI bus master devices directly on its secondary interface.

The 21152 allows the two PCI buses to operate concurrently. This means that a master and a target on the same PCI bus can communicate while the other PCI bus is busy. This traffic isolation may increase system performance in applications such as multimedia.




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