24C64

Features:

• Extended Power Supply Voltage
            Single Vcc for Read and Programming
           (Vcc = 2.7 V to 5.5 V)
• Low Power (Isb = 2a @ 5.5 V)
• Extended I²C Bus, 2-Wire Serial Interface
• Support Byte Write and Page Write (32 Bytes)
• Automatic Page write Operation (maximum 10 ms)
            Internal Control Timer
            Internal Data Latches for 32 Bytes
• Hardware Data Protection by Write Protect Pin
• High Reliability CMOS Technology with EEPROM Cell
           Endurance : 1,000,000 Cycles
           Data Retention : 100 Years


Pinout




Specifications

Storage:                 -65° C to 150° C
Under Bias:            -55° C to 125° C


Description

The Turbo IC 24C64 is a serial 64K EEPROM fabricated with Turbo's proprietary, high reliability, high performance CMOS technology. It's 64K of memory is organized as 8,192 x 8 bits. The memory is configured as 256 pages with each page containing 32 bytes. This device 24C64 offers significant advantages in low power and low voltage applications.

The Turbo IC 24C64 uses the extended I²C addressing protocol and 2-wire serial interface which includes a bidirectional serial data bus synchronized by a clock. It offers a flexible byte write and a faster 32-byte page write. The data in the upper quadrant of memory can be protected by a write protect pin.

The Turbo IC 24C64 is assembled in either a 8-pin PDIP or 8-pin SOIC package. Pin #1 (A0), #2 (A1), and #3 (A2) are device address input pins which are hardwired by the user. Pin #4 is the ground (V_ss). Pin #5 is the serial data (SDA) pin used for bidirectional transfer of data. Pin #6 is the serial clock (SCL) input pin. Pin #7 is the write protect (WP) input pin, and Pin #8 is the power supply (Vcc) pin.

All data is serially transmitted in bytes (8 bits) on the SDA bus. To access the Turbo IC 24C64 (slave) for a read or write operation, the controller (master) issues a start condition by pulling SDA from high to low while SCL is high. The master then issues the device address byte which consists of 1010 (A2) (A1) (A0) (R/W ). The 4 most significant bits (1010) are a device type code signifying an EEPROM device. The A[2:0] bits represent the input levels on the 3 device address input pins. The read/write bit determines whether to do a read or write operation. After each byte is transmitted, the receiver has to provide an acknowledge by pulling the SDA bus low on the ninth clock cycle. The acknowledge is a handshake signal to the transmitter indicating a successful data transmission.

For a write operation, the master issues a start condition, device address byte, 2 memory address bytes, and then up to 32 data bytes. The Turbo IC 24C64 acknowledges after each byte transmission. To terminate the transmission, the master issues a stop condition by pulling SDA from low to high while SCL is high.

For a read operation, the master issues a start condition and a device address byte. The Turbo IC 24C64 acknowledges, and then transmits a data byte, which is accessed from the EEPROM memory. The master acknowledges, indicating that it requires more data bytes. The Turbo IC 24C64 transmits more data bytes, with the memory address counter automatically incrementing for each data byte, until the master does not acknowledge, indicating that it is terminating the transmission. The master then issues a stop condition.