2SK2399

      The 2SK2399 is a Silicon N-Channel MOS Type Transistor designed for Chopper Regulator, DC/DC Converter and Motor Drive Applications.The 2SK2399 has 5 features including 4 V gate drive; Low drain-source ON-resistance : RDS (ON) = 0.17 (typ.);High forward transfer admittance : |Yfs| = 4.5 S (typ.);Low leakage current : IDSS = 100 A (max) (VDS = 100 V);Enhancement mode : Vth = 0.8~2.0 V (VDS = 10 V, ID = 1 mA).
      The absolute maximun ratings of the 2SK2399 are at Ta=25°C, Drain-source voltage VDSS is 100V;Drain-gate voltage (RGS = 20 k) VDGR is 100V;Gate-source voltage VGSS is ±20 V;drain Current ID is 5 A;drain power dissipation is 20W;channel temperature is 150°C;Storage temperature is -55 to +150°C.
      The 2SK2399 and 2SK2399 are non-inverting buffers, whereas the 2SK2399 and 2SK2399 are inverting buff- ers. These devices have two output enables, one enable (OE1) controls 4 gates and the other (OE2) controls the remaining 2 gates. Power MOS 7 is a new generation of low loss, high voltage, N-Channel enhancement mode power MOSFETS. Both conduction and switching losses are addressed with Power MOS 7TM by significantly lowering RDS(ON) and Qg. Power MOS 7TM combines lower conduction and switching losses along with exceptionally fast switching speeds inherent with APT's patented metal gate structure.  
      Two data address generators (DAGs) provide addresses for simultaneous dual operand fetches (from data memory and program memory). Each DAG maintains and updates four 16-bit address pointers. Whenever the pointer is used to access data (indirect addressing), it is pre- or post-modified by the value of one of four possible modify registers. A length value and base address may be associated with each pointer to implement automatic modulo addressing for circular buffers. Page registers in the DAGs allow circular addressing within 64K word bound- aries of each of the 256 memory pages, but these buffers may not cross page boundaries. Secondary registers duplicate all the primary registers in the DAGs; switching between primary and secondary registers provides a fast context switch.Precise control of the differential input voltage thresholds now allows for inclusion of 50 mV of input voltage hysteresis to improve noise rejection on slowly changing input signals. The input thresholds are still no more than 50 mV over the full input common-mode voltage range. 
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