32171

Note 1: This does not guarantee that the device can operate continuously at 125°C. If you are considering the use of this product in 125°C application, please consult Renesas.

32171 An interrupt from any internal peripheral I/O is checked to see whether or not to accept by comparing its ILEVEL value set in the Interrupt Control Register and the IMASK value of the Interrupt Request Mask Register. If its priority is higher than the IMASK value, the interrupt request is accepted. However, when multiple interrupt requests occur simultaneously, the interrupt controller resolves priority between these interrupt requests following the procedure described below.

(a) The ILEVEL values set in the Interrupt Control Register for each interrupt peripheral I/Os are compared with each other.

(b) If the ILEVEL values are the same, they are resolved according to the predetermined hardware priority.

(c) The ILEVEL value is compared with IMASK value.

When multiple interrupt requests occur simultaneously, the interrupt controller first compares their priority levels set in each Interrupt Control Register's ILEVEL bit to select an interrupt request which has the highest priority. If the interrupt requests have the same LEVEL value, they are resolved according to the hardware-fixed priority.

The interrupt request thus selected has its ILEVEL value compared with IMASK value and if its priority is higher than the IMASK value, the interrupt controller sends an EI request to the CPU.

Interrupt requests may be masked by setting the Interrupt Mask Register and the Interrupt Control Register's ILEVEL bit (level 7 = disabled) provided for each internal peripheral I/O and the PSW register IE bit.