32172

The microcomputer contains two blocks of TOM timers which are designed to reduce software load during motor control. This section explains an example for using TOM0 in motor control applications.

The three-phase motor control waveforms start TOM0 according to the TOM0 startup timing at a fixed period of 20 kHz generated by TID0. By using the TOM0's internal single-shot PWM function,the output waveform can easily be configured because the waveform data only needs to be stored at the necessary rewrite timing. The H and L transistor short-circuiting prevention time can be accomplished by changing the TOM0 setup time in software. Up to 8-phase motors can be controlled by a combined use of TID and TOM.

Note: This does not guarantee that the device will operate continuously at 125°C. If your application system is intended to operate at 125°C, please consult Mitsubishi.

32172 An interrupt from any internal peripheral I/O is accepted when its priority level is found to be higher than the IMASK value by comparing its ILEVEL set value in the Interrupt Control Register and the Interrupt Mask Register's IMASK value. However, if multiple interrupt requests occur at the same time, their priority is resolved following the procedure described below to determine which interrupt request to accept.

· Compare the ILEVEL values set with the Interrupt Control Registers for the respective internal peripheral I/Os
· If the ILEVEL values are the same, use the predetermined hardware priority to arbitrate
· Compare the ILEVEL and the IMASK values

When multiple interrupt requests occur at the same time, their priority levels set with ILEVEL of the respective Interrupt Control Registers are compared to select the interrupt request with the highest priority. If the selected interrupt requests have the same ILEVEL value, they are arbitrated according to the fixed hardware priority. The ILEVEL of the finally selected interrupt request is compared with the IMASK value, and if its priority is higher than the IMASK value, an EI request for it is sent to the CPU.

Interrupt requests may be masked setting the Interrupt Mask Register and the Interrupt Control Register ILEVEL bits (level 7 disables interrupt) provided for each internal peripheral I/O, as well as setting the PSW Register IE bit.