36Mb

The 36Mb IS61DDB41M36 and IS61DDB42M18 are synchronous, high-performance CMOS static random access memory (SRAM) devices. These SRAMs have a common I/O bus. The rising edge of K clock initiates the read/write operation, and all internal operations are self-timed. Refer to the Timing Reference Diagram for Truth Table on p.8 for a description of the basic operations of these DDR-II (Burst of 4) CIO SRAMs.

Read and write addresses are registered on alternating rising edges of 36Mb. Reads and writes are performed in double data rate. The following are registered internally on the rising edge of the K clock:

• Read and write addresses
• Address load
• Read/write enable
• Byte writes for burst addresses 1 and 3
• Data-in for burst addresses 1 and 3 The following are registered on the rising edge of the K clock:
• Byte writes for burst addresses 2 and 4
• Data-in for burst addresses 2 and 4

Byte writes can change with the corresponding datain to enable or disable writes on a per-byte basis. An internal write buffer enables the data-ins to be registered one cycle later than the write address. The first data-in burst is clocked one cycle later than the write command signal, and the second burst is timed to the following rising edge of the K clock. Two full  clock cycles are required to complete a write operation.

During the burst read operation, at the first and third bursts the data-outs are updated from output registers off the second and fourth rising edges of the C clock (starting 1.5 cycles later). At the second and fourth bursts, the data-outs are updated with the third and fifth rising edges of the corresponding C clock (see page 9). The K and K clocks are used to time the data-outs whenever the C and C clocks are tied high.

Two full clock cycles are required to complete a read operation The device is operated with a single +1.8V power supply and is compatible with HSTL I/O interfaces.