4000V/B/C/Z

      The 4000V/B/C/Z has 3 features.The first one is High Performance,fMAX= 400MHz maximum operating frequency,tPD= 2.5ns propagation delay,Up to four global clock pins with programmable clock polarity control,Up to 80 PTs per output.The second one is Ease of Design,Enhanced macrocells with individual clock,reset, preset and clock enable controls,Up to four global OE controls Individual local OE control per I/O pin Excellent First-Time-Fit and refit,Fast path, SpeedLocking Path, and wide-PT path,Wide input gating (36 input logic blocks) for fast,counters, state machines and address decoders.The third one of the 4000V/B/C/Z is Zero Power (ispMACH 4000Z) and Low Power (ispMACH 4000V/B/C),Typical static current 10A (4032Z),Typical static current 1.3mA (4000C),1.8V core low dynamic power,ispMACH 4000Z operational down to 1.6V VCC.
      The high performance 4000V/B/C/Z from Lattice offers a SuperFAST CPLD solution. The 4000V/B/C/Z is a blend of Lattice's two most popular architectures: the ispLSI 2000 and ispMACH 4A. Retaining the best of both families,the ispMACH 4000 architecture focuses on significant innovations to combine the highest performance with low power in a flexible CPLD family.
      The 4000V/B/C/Z combines high speed and low power with the flexibility needed for ease of design. With its robust Global Routing Pool and Output Routing Pool, this family delivers excellent First-Time-Fit, timing predictability,routing, pin-out retention and density migration.The 4000V/B/C/Z offers densities ranging from 32 to 512 macrocells. There are multiple density-I/O combinations in Thin Quad Flat Pack (TQFP), Chip Scale BGA (csBGA) and Fine Pitch Thin BGA (ftBGA) packages ranging from 44 to 256 pins/balls. Table 1 shows the macrocell, package and I/O options, along with other key parameters.The ispMACH 4000 family has enhanced system integration capabilities. 4000V/B/C/Z supports 3.3V (4000V), 2.5V (4000B) and 1.8V (4000C/Z) supply voltages and 3.3V, 2.5V and 1.8V interface voltages. Additionally, inputs can be safely driven up to 5.5V when an I/O bank is configured for 3.3V operation, making this family 5V tolerant. The 4000V/B/C/Z also offers enhanced I/O features such as slew rate control, PCI compatibility, bus-keeper latches, pull-up resistors, pull-down resistors, open drain outputs and hot socketing. The 4000V/B/C/Z members are 3.3V/2.5V/1.8V in-system programmable through the IEEE Standard 1532 interface. IEEE Standard 1149.1 boundary scan testing capability also allows product testing on automated test equipment. The 1532 interface signals TCK,TMS, TDI and TDO are referenced to VCC (logic core).