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Xilinx introduces the XC18V00 series of in-system programmable configuration PROMs (Figure 1). XC18V00 series in this 3.3V family include a 4-megabit, a 2-megabit, a 1-megabit, and a 512-kilobit PROM that provide an easy-to-use, cost-effective method for re-programming and storing Xilinx FPGA configuration bitstreams. When the FPGA is in Master Serial mode, XC18V00 series generates a configuration clock that drives the PROM. A short access time after CE and OE are enabled, data is available on the PROM DATA (D0) pin that is connected to the FPGA DIN pin. New data is available a short access time after each rising clock edge. The FPGA XC18V00 series generates the appropriate number of clock pulses to complete the configuration.

When the XC18V00 series FPGA is in Slave Serial mode, the PROM and the FPGA are clocked by an external clock. When the FPGA is in Slave-Parallel or Slave-SelectMAP Mode, an external oscillator generates the configuration clock that drives the PROM and the FPGA. After CE and OE are enabled, data is available on the PROMs DATA (D0-D7) pins. New data is available a short access time after each rising clock edge. The data is clocked into the FPGA on the following rising edge of the CCLK. A free-running oscillator of XC18V00 series can be used in the Slave-Parallel or Slave-SelecMAP modes.

XC18V00 series can be concatenated by using the CEO output to drive the CE input of the following device. The clock inputs and the DATA outputs of all PROMs in this chain are interconnected. XC18V00 series are compatible and can be cascaded with other members of the family or with the XC17V00 one-time programmable Serial PROM family.