Purchase 54F407, In-stock 54F407 From SeekIC.
Part Number: 54F407
Description: The 'F407 Data Access Register (DAR) performs memory address arithmetic for RAM resident stack applica...
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54F407
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DataSheet
General Description
54F407 General Description
The 'F407 Data Access Register (DAR) performs memory address arithmetic for RAM resident stack applications. It contains three 4-bit registers intended for Program Counter (R0), Stack Pointer (R1), and Operand Address (R2). The 'F407 implements 16 instructions which allow either pre- or post-decrement/increment and register-to-register transfer in a single clock cycle. It is expandable in 4-bit increments and can operate at a 30 MHz microinstruction rate on a 16-bit word. The TRI-STATEÉ outputs are provided for busoriented applications. The 'F407 is fully compatible with all TTL families.
54F407 Maximum Ratings
Storage Temperature -65 to a150
Ambient Temperature under Bias -55 to a125
Junction Temperature under Bias -55 to a175
VCC Pin Potential toGround Pin -0.5V to a7.0V
Input Voltage (Note 2) -0.5V to a7.0V
Input Current (Note 2) -30 mA to +5.0 mA
Voltage Applied to Output
in HIGH State (with VCC e 0V)
Standard Output -0.5V to VCC
TRI-STATE Output -0.5V to a5.5V
Current Applied to Output
in LOW State (Max) twice the rated IOL (mA)
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
54F407 Features
· High-speedÐgreater than a 30 MHz microinstruction rate
· Three 4-bit registers
· 16 instructions for register manipulation
· Two separate output ports, one transparent
· Relative addressing capability
· TRI-STATE Outputs
· Optional pre- or post- arithmetic
· Expandable in multiples of four bits
· 24-pin slim package
· 9407 replacement
· Three 4-bit registers
· 16 instructions for register manipulation
· Two separate output ports, one transparent
· Relative addressing capability
· TRI-STATE Outputs
· Optional pre- or post- arithmetic
· Expandable in multiples of four bits
· 24-pin slim package
· 9407 replacement
54F407 Connection Diagram
54F407DMQB
PDF/DataSheet Download
- Datasheet: 54F407DMQB
- File Size: 175601 KB
- Manufacturer: NSC
- Click here to Download
- ·54F00
- NSC [National Semiconductor]
- Quad 2-Input NAND Gate
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- ·54F00DM
- NSC [National Semiconductor]
- Quad 2-Input NAND Gate
- 112191 KB
- ·54F00FM
- NSC [National Semiconductor]
- Quad 2-Input NAND Gate
- 112191 KB
- ·54F00LM
- NSC [National Semiconductor]
- Quad 2-Input NAND Gate
- 112191 KB
- ·54F02
- NATIONAL
- Quad 2-Input NOR Gate
- 98391 KB
- ·54F02DM
- NSC [National Semiconductor]
- Quad 2-Input NOR Gate
- 97524 KB
- ·54F02FM
- NSC [National Semiconductor]
- Quad 2-Input NOR Gate
- 97524 KB
- ·54F02LM
- NSC [National Semiconductor]
- Quad 2-Input NOR Gate
- 97524 KB
54F407 Relative Products
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54F38
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54F377
The 54F377 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) input loads all flip-flops simultaneously, when the Clock Enable (CE) is LOW.The register 54F377 is fully edge-triggered. The state ...
54F374
The 54F374 is a high-speed, low-power octal D-type flip-flop featuring separate D-type inputs for each flip-flop and TRI-STATE outputs for bus-oriented applications. A buffered Clock (CP) and Output Enable (OE#) are common to all flip-flops.
54F373
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