Purchase 54F413D-CQB, In-stock 54F413D-CQB From SeekIC.
Part Number: 54F413D-CQB
Description: The 'F413 is an expandable fall-through type high-speed First-In First-Out (FIFO) buffer memory organi...
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54F413D-CQB
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DataSheet
General Description
54F413D-CQB General Description
The 'F413 is an expandable fall-through type high-speed First-In First-Out (FIFO) buffer memory organized as 64 words by four bits. The 4-bit input and output registers record and transmit, respectively, asynchronous data in parallel form. Control pins on the input and output allow for handshaking and expansion. The 4-bit wide, 62-bit deep fallthrough stack has self-contained control logic.
54F413D-CQB Maximum Ratings
|
Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias Plastic VCC Pin Potential to Ground Pin Input Voltage (Note 2) Input Current (Note 2) Voltage Applied to Output in HIGH State (with VCC = 0V) Standard Output TRI-STATE Output Current Applied to Output in LOW State (Max) ESD Last Passing Voltage (Min) |
- 65 to + 150 -55 to + 125 -55 to + 175 -55 to +150 -0.5V to +7.0V -0.5V to + 7.0V -30 mA to + 5.0 mA -0.5V to VCC -0.5V to + 5.5V twice the rated IOL (mA) 4000V |
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
54F413D-CQB Features
· Separate input and output clocks
· Parallel input and output
· Expandable without external logic
· 15 MHz data rate
· Supply current 160 mA max
· Available in SOIC, (300 mil only)
· Parallel input and output
· Expandable without external logic
· 15 MHz data rate
· Supply current 160 mA max
· Available in SOIC, (300 mil only)
54F413D-CQB Connection Diagram
54F413D-CQB
PDF/DataSheet Download
- Datasheet: 54F413D-CQB
- File Size: 115802 KB
- Manufacturer: NSC [National Semiconductor]
- Click here to Download
- ·54F00
- NSC [National Semiconductor]
- Quad 2-Input NAND Gate
- 112191 KB
- ·54F00DM
- NSC [National Semiconductor]
- Quad 2-Input NAND Gate
- 112191 KB
- ·54F00FM
- NSC [National Semiconductor]
- Quad 2-Input NAND Gate
- 112191 KB
- ·54F00LM
- NSC [National Semiconductor]
- Quad 2-Input NAND Gate
- 112191 KB
- ·54F02
- NATIONAL
- Quad 2-Input NOR Gate
- 98391 KB
- ·54F02DM
- NSC [National Semiconductor]
- Quad 2-Input NOR Gate
- 97524 KB
- ·54F02FM
- NSC [National Semiconductor]
- Quad 2-Input NOR Gate
- 97524 KB
- ·54F02LM
- NSC [National Semiconductor]
- Quad 2-Input NOR Gate
- 97524 KB
54F413D-CQB Relative Products
54F407
The 54F407 Data Access Register (DAR) performs memory address arithmetic for RAM resident stack applications. It contains three 4-bit registers intended for Program Counter (R0), Stack Pointer (R1), and Operand Address (R2). The 54F407 implements 16 instruct...
54F402
The 54F402 expandable Serial Data Polynomial generator/checker is an expandable version of the 'F401. It provides an advanced tool for the implementation of the most widely used error detection scheme in serial digital handling systems.A 4-bit control input ...
54F38
This 54F38 contains four independent gates, each of which performs the logic NAND function. The open-collector outputs require external pull-up resistors for proper logical operation.
54F377
The 54F377 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) input loads all flip-flops simultaneously, when the Clock Enable (CE) is LOW.The register 54F377 is fully edge-triggered. The state ...
54F374
The 54F374 is a high-speed, low-power octal D-type flip-flop featuring separate D-type inputs for each flip-flop and TRI-STATE outputs for bus-oriented applications. A buffered Clock (CP) and Output Enable (OE#) are common to all flip-flops.
54F373
The 54F373 consists of eight latches with TRI-STATE outputs for bus organized system applications. The flip-flops 54F373 appear transparent to the data when Latch Enable (LE) is HIGH. When LE is LOW, the data that meets the setup times is latched. Data appea...
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