Purchase 54LS114, In-stock 54LS114 From SeekIC.
Part Number: 54LS114
Description: The 'LS114 features individual J, K and set inputs and common clock and common clear inputs. When the ...
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54LS114
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DataSheet
General Description
54LS114 General Description
The 'LS114 features individual J, K and set inputs and common clock and common clear inputs. When the clock goes HIGH the inputs are enabled and data will be accepted. The logic level of the J and K inputs may be allowed to change when the Clock Pulse is HIGH and the bistable will perform according to the truth table as long as the minimum setup times are observed. Input data is transferred to the outputs on the negative-going edge of the clock pulse.
54LS114 Maximum Ratings
Supply Voltage ....................................................................................7V
Input Voltage ......................................................................................7V
Operating Free Air Temperature Range
54LS ..........................................................................-55 to +125
Storage Temperature Range .........................................-65 to +150
Input Voltage ......................................................................................7V
Operating Free Air Temperature Range
54LS ..........................................................................-55 to +125
Storage Temperature Range .........................................-65 to +150
54LS114 Connection Diagram
54LS114
PDF/DataSheet Download
- Datasheet: 54LS114
- File Size: 120921 KB
- Manufacturer: NSC [National Semiconductor]
- Click here to Download
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54LS114 Relative Products
54LS113
The 54LS113 offers individual J, K, Set and Clock inputs. When the clock goes HIGH the inputs are enabled and data may be entered. The logic level of the J and K inputs may be changed when the clock pulse of 54LS113 is HIGH and the bistable will perform acco...
54LS11
This 54LS11 contains three independent gates each of which performs the logic AND function.
54LS109
This 54LS109 contains two independent positive-edge-triggered J-K flip-flops with complementary outputs. The J and K data is accepted by the flip-flop on the rising edge of the clock pulse. The triggering of 54LS109 occurs at a voltage level and is not direc...
54LS10
This 54LS10 contains three independent gates each of which performs the logic NAND function.
54LS09FMQB
The 54LS09FMQB contains four independent gates each of which performs the logic AND function.The open-collector outputs require external pull-up resistors for proper logical operations.Features of the 54LS09FMQB is alternate military/aerospace device is avai...
54LS08
This 54LS08 contains four independent gates each of which performs the logic AND function.
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