74ABT16260

Features:

• ESD protection exceeds 2000V per Mil-Std-883C, Method 3015;exceeds 200V using machine model (C = 200pF, R = 0).
• Latch-up performance exceeds 500mA per JEDEC Standard JESD-17.
• Distributed VCC and GND pin configuration minimizes high-speed switching noise.
• Flow-through architecture optimizes PCB layout.
• High-drive outputs (32mA IOH, 64mA I_OL).
• 74ABTH16260 incorporates bus-hold inputs which eliminate the need for external pull-up resistors.
• Package options:
56-pin plastic Shrink Small-Outline Package (SSOP)
56-pin plastic Thin Shrink Small-Outline Package (TSSOP)



Pinout




Specifications

SYMBOL	PARAMETER	CONDITIONS	LIMITS		UNIT
			MIN	MAX
VCC	Supply voltage range		0.5	V	V
VI	Input voltage range	see Note 2	0.5	7	V
VO	Voltage range applied to any output in the high state or power-off state		0.5	5.5	V
IO	Current into any output in the low state			128	mA
IIK	Input clamp current	VI < 0		18	mA
IOK	Output clamp current	VO < 0		50	mA
	Maximum power dissipation at Tamb = 55°C (in still air)	see Note 3		1.4	W
Tstg	Storage temperature range		65	+150	°C

Description

   The 74ABT16260/74ABTH16260 is a 12-bit to 24-bit multiplexed D-type latch used in applications where two separate data paths must be multiplexed onto, or demultiplexed from, a single data path.Typical applications include multiplexing and/or demultiplexing of address and data information in microprocessor or bus-interface
applications. The 74ABT16260 is alto useful in memory-interleaving applications.

   Three 12-bit I/O ports (A1A12, 1B11B12, and 2B12B12) are available for address and/or data transfer. The output enable (OE1B ,OE2B , and OEA ) inputs control the bus transceiver functions. The OE1B and OE2B control signals also allow bank control in the A to B direction.

   Address and/or data information of the 74ABT16260 can be stored using the internal storage latches. The latch enable (LE1B, LE2B, LEA1B, and LEA2B) inputs are used to control data storage. When the latch enable input is high, the latch is transparent. When the latch enable input goes low, the data present at the inputs is latched and remains
latched until the latch enable input is returned high.

   To ensure the high-impedance state during power-up or power-down, OE should be tied to VCC through a pull-up resistor; the minimum value of the resistor is determined by the current sinking capability of the driver.

   The 74ABT16260 incorporates the bus hold feature. The 74ABT does not include bus hold feature. Both parts are available in 56-pin SSOP and TSSOP.