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Part Number: 74AC11175

 

 

 

 

Description: These positive-edge-triggered flipflops implement D-type flip-flop logic with a direct clear input. In...


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74AC11175 General Description


These positive-edge-triggered flipflops implement D-type flip-flop logic with a direct clear input. Information at the D inputs that meets the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock input is at either the high or low level, the D input signal has no effect at the output.

The 54AC11175 is characterized for operation over the full military temperature range of 55°C to 125°C. The 74AC11175 is characterized for operation from 40°C to 85°C.

74AC11175 Maximum Ratings

Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . 0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . 0.5 V to VCC + 0.5 V
Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . 0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . .  . . . . ±20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . .   . . . ±50 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . .   . . ±100 mA
Storage temperature range . . . . . . . . . . . . . . . . . . .. . . . . . . .. 65°C to 150°C
‡ Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

74AC11175 Features

• Applications Include: Buffer/Storage Registers, Shift Registers, Pattern Generators
• Flow-Through Architecture Optimizes PCB Layout
• Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise
• EPIC™ (Enhanced-Performance Implanted CMOS) 1-m Process
• 500-mA Typical Latch-Up Immunity at 125°C
• Package Options Include Plastic Small-Outline Packages, Ceramic Chip Carriers, and Standard Plastic and Ceramic 300-mil DIPs

74AC11175 Connection Diagram

74AC11175  Connection Diagram

74AC11175 datasheet

74AC11175
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