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74AHCT594

Features: Wide supply voltage range from 2.0 V to 5.5 V 8-bit serial-in, parallel-out shift register with storageIndependent direct overriding clears on shift and storage registersIndependent clocks for shift and storage registers Latch-up performance exceeds 100 mA per JESD 78 Class II Input leve...

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74AHCT594: Features: Wide supply voltage range from 2.0 V to 5.5 V 8-bit serial-in, parallel-out shift register with storageIndependent direct overriding clears on shift and storage registersIndependent clocks...

74AHCT594 Data Sheet

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Part Number:
74AHCT594
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

 Wide supply voltage range from 2.0 V to 5.5 V
  8-bit serial-in, parallel-out shift register with storage
 Independent direct overriding clears on shift and storage registers
 Independent clocks for shift and storage registers
  Latch-up performance exceeds 100 mA per JESD 78 Class II
  Input levels:
  CMOS levels: 74AHC594 only
 TTL levels: 74AHCT594 only
  ESD protection:
  HBM JESD22-A114-C exceeds 2000 V
  MM JESD22-A115-A exceeds 200 V
 CDM JESD22-C101-C exceeds 1000 V
 Specified from -40 °C to +85 °C and from -40 °C to +125 °C


Application

 Serial-to parallel data conversion
 Remote control holding register


Specifications

Symbol Parameter Conditions
Min
Max
Unit
VCC supply voltage  
-0.5
+7.0
V
VI input voltage  
-0.5
+7.0
V
IIK input clamping current VI < -0.5 V
-20
mA
IOK output clamping current VO < -0.5 V or VO > VCC + 0.5 V
±20
mA
IO output current VO = -0.5 V to VCC + 0.5 V
±25
mA
ICC quiescent supply current  
75
mA
IGND ground current  
-75
mA
Tstg storage temperature  
-65
+150
Ptot total power dissipation Tamb = -40 to +125
500
mW



Description

The 74AHC594; 74AHCT594 is a high-speed Si-gate CMOS device and is pin compatible with Low-Power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7A.

The 74AHC594; 74AHCT594 is an 8-bit, non-inverting, serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. Separate clocks (SHCP and STCP) and direct overriding clears (SHR and STR) are provided on both the shift and storage registers. A serial output (Q7S) is provided for cascading purposes.

Both the shift and storage register clocks of the 74AHCT594 are positive-edge triggered. If the user wishes to connect both clocks together, the shift register will always be one count pulse ahead of the storage register.




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