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74AUP1G17

Features: `Wide supply voltage range from 0.8 V to 3.6 V`High noise immunity`Complies with JEDEC standards:`JESD8-12 (0.8 V to 1.3 V)`JESD8-11 (0.9 V to 1.65 V)`JESD8-7 (1.2 V to 1.95 V)`JESD8-5 (1.8 V to 2.7 V)`JESD8-B (2.7 V to 3.6 V)`ESD protection:`HBM JESD22-A114-C exceeds 2000 V`MM JESD22-A1...

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SeekIC No. : 004249527 Detail

74AUP1G17: Features: `Wide supply voltage range from 0.8 V to 3.6 V`High noise immunity`Complies with JEDEC standards:`JESD8-12 (0.8 V to 1.3 V)`JESD8-11 (0.9 V to 1.65 V)`JESD8-7 (1.2 V to 1.95 V)`JESD8-5 (1....

74AUP1G17 Data Sheet

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Part Number:
74AUP1G17
Supply Ability:
5000

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  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2025/12/28

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Product Details

Description



Features:

`Wide supply voltage range from 0.8 V to 3.6 V
`High noise immunity
`Complies with JEDEC standards:
`JESD8-12 (0.8 V to 1.3 V)
`JESD8-11 (0.9 V to 1.65 V)
`JESD8-7 (1.2 V to 1.95 V)
`JESD8-5 (1.8 V to 2.7 V)
`JESD8-B (2.7 V to 3.6 V)
`ESD protection:
`HBM JESD22-A114-C exceeds 2000 V
`MM JESD22-A115-A exceeds 200 V
`CDM JESD22-C101-C exceeds 1000 V
`Low static power consumption; ICC = 0.9 mA (maximum)
`Latch-up performance exceeds 100 mA per JESD 78 Class II
`Inputs accept voltages up to 3.6 V
`Low noise overshoot and undershoot < 10 % of VCC
`IOFF circuitry provides partial Power-down mode operation
`Multiple package options
`Specified from -40 to +85 and -40 to +125


Pinout

Connection Diagram


Specifications

Symbol Parameter Conditions Min Max Unit
Vcc supply voltage   -0.5 +4.6 V
VI input voltage   - -50 V
IIk input clamping current VI < -0.5 V*1 -0.5 +4.6 V
IoK output clamping current VO < -0.5 V or VO > VCC + 0.5 V*1 - ±50 mA
VO output current active mode -0.5 VCC + 0.5 mA
Power-down mode   +4.6
IO supply current VO = 0 V to Vcc -0.5 ±20 mA
ICC ground current   - -50 mAc
IANG ground current     -50 mA
Tstg storage temperature   -65 +150
PTOT total power dissipation Tamb = -40 to +125   250 mW
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For TSSOP5 packages: above 87.5 the value of Ptot derates linearly with 4.0 mW/K.
For XSON6 packages: above 45 the value of Ptot derates linearly with 2.4 mW/K.


Description

The 74AUP1G17 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families.

Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V.

The 74AUP1G17 ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V.

The 74AUP1G17 is fully specified for partial Power-down applications using IOFF.

The IOFF circuitry of the 74AUP1G17 disables the output, preventing the damaging backflow current through the device when it is powered down.

The 74AUP1G17 provides the single Schmitt-trigger buffer. It is capable of transforming slowly changing input signals into sharply defined, jitter-free output signals.




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