74AUP1G74

The 74AUP1G74 is a high-performance, low-power, low-voltage, Si-gate CMOS device,
superior to most advanced CMOS compatible TTL families.

Schmitt-trigger action of the 74AUP1G74 at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V. This device ensures a very low static and dynamic power consumption across the ntire VCC range from 0.8 V to 3.6 V.

The 74AUP1G74 is fully specified for partial Power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current  hrough the device when it is powered down.

The 74AUP1G74 provides the single positive-edge triggered D-type flip-flop with ndividual data (D) input, clock (CP) input, set (SD) and reset (RD) inputs and omplementary Q and Q outputs. The set and reset are asynchronous active LOW inputs and operate independently of the clock input. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. The D input must  be stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation.