74F273A

• High impedance inputs for reduced loading (20mA in Low and High states)
• Ideal buffer for MOS microprocessor or memory
• Eight edgetriggered Dtype flipflops
• Buffered common clock
• Buffered asynchronous Master Reset
• See 74F377A for clock enable version
• See 74F373 for transparent latch version
• See 74F374 for 3State version

The 74F273A has eight edgetriggered Dtype flipflops with individual D inputs and Q outputs. The common uffered Clock (CP) and Master Reset (MR) inputs load and reset (clear) all flipflops simultaneously.

The register of the 74F273A is fully edgetriggered. The state of each D input, one setup time before the LowtoHigh clock transition, is transferred to the corresponding flipflop's Q output.

All outputs of the 74F273A will be forced Low independently of Clock or Data inputs by a Low voltage level on the MR input. The device is useful for applications where the true output only is required and the CP and MR are common to all elements.