74F321RGTC

The 74F321RGTC is designed as one kind of 32Mx72bits Dynamic RAM high density memory device that consists of thirty-six CMOS 16Mx4bits DRAMs in SOJ 400mil packages and one 1K/2K EEPROM for SPD in 8-pin SOP package mounted on a 168-pin glassepoxy substrate.

Features of the 74F321RGTC are:(1)New JEDEC standard proposal without buffer; (2)Serial Presence Detect with EEPROM; (3)Extended Data Out Mode Operation; (4)CAS-before-RAS Refresh capability; (5)RAS-only and Hidden refresh capability; (6)LVTTL compatible inputs and outputs; (7)Single +3.3V?.3V power supply; (8)PCB : Height(1625mil), double sided component. The absolute maximum ratings of the 74F321RGTC can be summarized as:(1)Voltage on any pin relative VSS: -0.5 to +4.6 V;(2)Voltage on VCC supply relative to VSS: -0.5 to +4.6 V;(3)Storage Temperature: -55 to +150 ;(4)Power Dissipation: 36 W;(5)Short Circuit Output Current: 50 mA.

The electrical characteristics of this device can be summarized as:(1)Random read or write cycle time: 84 to 104 ns;(2)Read-modify-write cycle time: 128 to 153 ns;(3)Access time from RAS: 50 to 60 ns;(4)Access time from CAS: 13 to 15 ns;(5)Access time from column address: 25 to 30 ns;(6)CAS to output in Low-Z: 3 ns;(7)OE to output in Low-Z: 3 ns;(8)Output buffer turn-off delay from CAS: 3 to 13 ns. If you want to know more information about it, please download the datasheet in www.seekic.com or www.chinaicmart.com .