74F646

    The 74F646 transceivers/registers consist of bus transceiver circuits with 3state outputs, Dtype flipflops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or the internal registers. Data on the A or B bus will be clocked into the registers as the appropriate clock pin goes high. Output enable (OE) and DIR  pins are provided to control the transceiver function. In the transceiver mode of the 74F646, data present at the high impedance port may be stored in either the A or B register or both.

    The select (SAB, SBA) pins determine whether data is stored or transferred through the device in realtime. The DIR determines which bus will receive data when the OE is active low. In the isolation mode (OE = high), data from bus A may be stored in the B register and/or data from bus B may be stored in the A register. When an output function is disabled, the input function of the 74F646 is still enabled and may be used to store and transmit data. Only one of the two buses, A or B may be driven at a time.