Features: 0.5 MICRON CMOS Technology
High-speed, low-power CMOS replacement for ABT functions
Typical tSK(o) (Output Skew) < 250ps
Low input and output leakage`1`A (max.)
ESD > 2000V per MIL-STD-883, Method 3015;> 200V using machine model (C = 200pF, R = 0)
Packages include 25 mil pitch SSOP, 19.6 mil pitch TSSOP, 15.7 mil pitch TVSOP and 25 mil pitch Cerpack
Extended commercial range of -40`C to +85`C
Balanced Output Drivers: `24mA (commercial),`16mA (military)
Reduced system switching noise
Typical VOLP (Output Ground Bounce) < 0.6V at VCC = 5V,TA = 25`C
Pinout
Specifications
|
Symbol |
Description |
Max. |
Unit |
|
VTERM(2) |
Terminal Voltage with Respect to
GND |
0.5 to +7.0 |
V |
|
VTERM(3) |
Terminal Voltage with Respect to
GND |
0.5 to
VCC +0.5 |
V |
|
TSTG |
Storage Temperature |
65 to +150 |
°C |
|
IOUT |
DC Output Current |
60 to +120 |
mA |
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. All device terminals except FCT162XXXT Output and I/O terminals.
3. Output and I/O terminals for FCT162XXXT.DescriptionThe 74FCT162501AT 18- bit registered transceivers are built using advanced dual metalCMOS technology. These high-speed, low-power 18-bit registered bus transceivers combine D-type latches and D-type flip-flops to allow data flow in transparent, latched and clocked modes. Data flow in each direction is controlled by outputenable (OEAB and OEBA), latch enable (LEAB and LEBA) and clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the device operates in transparent mode when LEAB is HIGH. When LEAB is LOW, the A data is latched if CLKAB is held at a HIGH or LOW logic level. If LEAB is LOW, the A bus data is stored in the latch/flip-flop on the LOW-to-HIGH transition of CLKAB. OEAB is the output enable for the B port. Data flow from the B port to the A port is similar but requires using OEBA, LEBA and CLKBA. Flow-through organization of signal pins simplifies layout. All inputs are designed with hysteresis for improved noise margin.
The 74FCT162501AT are ideally suited for driving high-capacitance loads and low-impedance backplanes. The output buffers are designed with power off disable capability to allow "live insertion" of boards when used as backplane drivers.
The 74FCT162501AT have balanced output drivewith current limiting resistors. This offers low ground bounce, minimal undershoot, and controlled output fall timesreducing the need for external series terminating resistors. The FCT162501AT/CT/ET are plug-in replacements for the FCT16501AT/CT/ET and ABT16501 for on-board bus interface applications.
The 74FCT162501AT have "Bus Hold" which retains the input's last state whenever the input goes to high impedance. This prevents "floating" inputs and eliminates the need for pull-up/down resistors.
74FCT162501AT Data Sheet
