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74HC237

Features: ·Combines 3-to-8 decoder with 3-bit latch·Multiple input enable for easy expansion or independent controls·Active HIGH mutually exclusive outputs·Low-power dissipation·Complies with JEDEC standard no. 7A·ESD protection:HBM EIA/JESD22-A114-B exceeds 2000 VMM EIA/JESD22-A115-A exceeds 200 ...

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SeekIC No. : 004250724 Detail

74HC237: Features: ·Combines 3-to-8 decoder with 3-bit latch·Multiple input enable for easy expansion or independent controls·Active HIGH mutually exclusive outputs·Low-power dissipation·Complies with JEDEC ...

74HC237 Data Sheet

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Part Number:
74HC237
Supply Ability:
5000

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Product Details

Description



Features:

·Combines 3-to-8 decoder with 3-bit latch
·Multiple input enable for easy expansion or independent controls
·Active HIGH mutually exclusive outputs
·Low-power dissipation
·Complies with JEDEC standard no. 7A
·ESD protection:
HBM EIA/JESD22-A114-B exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V.
·Multiple package options
·Specified from -40 °C to +80 °C and from -40 °C to +125 °C.


Specifications

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
VCC supply voltage   -0.5 +7.0 V
IIK input diode current VI < -0.5 V or VI > VCC + 0.5 V - ±20 mA
IOK output diode current VO < -0.5 V or VO > VCC + 0.5 V - ±20 mA
IO output source or sink current VO = -0.5 V to VCC + 0.5 V - ±25 mA
ICC VCC or GND current   - ±50 mA
Tstg storage temperature   -65 +150 °C
Ptot
 power dissipation        
DIP16 package   [1] - 750 mW
SO16 and SSOP16
packages		   [2] - 500 mW

[1] Above 70 °C: Ptot derates linearly with 12 mW/K.
[2] Above 70 °C: Ptot derates linearly with 8 mW/K.


Description

The 74HC237 is a high-speed Si-gate CMOS device and is pin compatible with low power Schottky TTL (LSTTL). The 74HC237 is specified in compliance with JEDEC standard no. 7A.

The 74HC237 is a 3-to-8 line decoder, demultiplexer with latches at the three address inputs (An). The 74HC237 essentially combines the 3-to-8 decoder function with a 3-bit storage latch. When the latch is enabled (LE = LOW), the 74HC237 acts as a 3-to-8 active LOW decoder. When the latch enable (LE) goes from LOW-to-HIGH, the last data present at the inputs before this transition, is stored in the latches. Further address changes are ignored as long as LE remains HIGH.

The output enable input (E1 and E2) controls the state of the outputs independent of the address inputs or latch operation. All outputs are HIGH unless E1 is LOW and E2 is HIGH.

The 74HC237 is ideally suited for implementing non-overlapping decoders in 3-state systems and strobed (stored address) applications in bus oriented systems.




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