74HC4059

The 74HC4059 is high-speed Si-gate CMOS devices and are pin compatible with the "4059" of the "4000B" series. They are specified in compliance with JEDEC standard no. 7A.

The 74HC4059 is divide-by-n counters which can be programmed to divide an input frequency by any number (n) from 3 to 15 999. There are four operating modes, timer, divide-by-n, divide-by-10 000 and master preset, which are defined by the mode select inputs (K_a to K_c) and the latch enable input (LE) as shown in the Function table.

The complete counter consists of a first counting stage, an intermediate counting stage and a fifth counting stage. The first counter stage consists of four independent flip-flops. Depending on the divide-by-mode, at least one flip-flop is placed at the input of the intermediate stage (the remaining flip-flops are placed at the fifth stage with a place value of thousands). The intermediate stage consists of three cascaded decade counters, each containing four flip-flops.

All flip-flops of the 74HC4059 can be preset to a desired state by means of the JAM inputs (J₁ to J₁₆), during which the clock input (CP) will cause all stages to count from n to zero. The zero-detect circuit will then cause all stages to return to the JAM count, during which an output pulse is generated. In the timer mode, after an output pulse is generated, the output pulse remains HIGH until the latch input (LE) goes LOW. The counter of the 74HC4059 will advance, even if LE is HIGH and the output is latched in the HIGH state.