74HC563 General Description
The M54/74HC563 andM54HC573 are high speed CMOS OCTAL LATCH WITH 3-STATE OUTPUTS fabricated with in silicon gate C2MOS technology.
These ICs archive the high speed operation similar to equivalent LSTTL while maintaning the CMOS low power dissipation.
These 8 bit D-Type latches are controlled by a latch enable input (LE) and a output enable input (OE). While the LE input is held at a high level, the Q outputs will follow the data input precisely or inversely. When the LE is taken low, the Q outputs will be latched precisely or inversely at the logic level of D input data. While the OE input is at low level, the eight outputs will be in a normal logic state (high or low logic level) and while high level the outpts will be in a high impedance state.
The application designer has a choise of combination of inverting and non inverting outputs.
The three state output configuration and the wide choise of outline make bus organized system simple.
All inputs are equipped with protection circuits against discharge and transient excess voltage.
74HC563 Features
HIGH SPEED
tPD = 13 ns (TYP.) AT VCC = 5 V LOWPOWER DISSIPATION
ICC = 4 mA (MAX.) AT TA = 25 °C HIGH NOISE IMMUNITY
VNIH = VNIL = 28 % VCC (MIN.) OUTPUT DRIVE CAPABILITY
15 LSTTL LOADS SYMMETRICAL OUTPUT IMPEDANCE
IOL = zIOHz= 6 mA (MIN.) BALANCEDPROPAGATION DELAYS
tPLH = tPHL WIDE OPERATING VOLTAGE RANGE
VCC (OPR) = 2 V TO 6 V PIN AND FUNCTION COMPATIBLE WITH 54/74LS563/573
74HC563 Connection Diagram
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