74HCT4017

The 74HCT4017 is high-speed Si-gate CMOS devices and are pin compatible with the "4017" of the "4000B" series. They are specified in compliance with JEDEC standard no. 7A.

The 74HCT4017 is 5-stage Johnson decade counters with 10 decoded active HIGH outputs (Q₀ to Q₉), an active LOW output from the most significant flip-flop (Q5-9), active HIGH and active LOW clock inputs (CP₀ andCP₁) and an overriding asynchronous master reset input (MR).

The counter of the 74HCT4017 is advanced by either a LOW-to-HIGH transition at CP₀ while CP₁ is LOW or a HIGH-to-LOW transition at CP₁ while CP₀ is HIGH (see also function table).

When cascading counters, the Q₅-9 output of the 74HCT4017, which is LOW while the counter is in states 5, 6, 7, 8 and 9, can be used
to drive the CP₀ input of the next counter.

A HIGH on MR resets the counter of the 74HCT4017 to zero (Q₀ = Q_5-9 = HIGH; Q₁ to Q₉ = LOW) independent of the clock inputs (CP₀ and CP₁).

Automatic code correction of the counter is provided by an internal circuit: following any illegal code the counter returns to a proper counting mode within 11 clock pulses.