74LCX373M

Minimum Operating Temperature : - 40 C
Polarity : Non-Inverting
Supply Voltage - Min : 2 V
Maximum Operating Temperature : + 85 C
Number of Output Lines : 8
Low Level Output Current : 32 mA
Number of Circuits : 1
Packaging : Tube
High Level Output Current : - 24 mA
Supply Voltage - Max : 3.6 V
Logic Type : CMOS
Package / Case : SOP-20
Propagation Delay Time : 9 ns at 2.7 V, 8 ns at 3 V to 3.6 V
Logic Family : 74LCX


Features:

· 5V TOLERANT INPUTS AND OUTPUTS
· HIGH SPEED : tPD = 8.0 ns (MAX.) at VCC = 3V
· POWER DOWN PROTECTION ON INPUTS AND OUTPUTS
· SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 24mA (MIN) at VCC = 3V
· PCI BUS LEVELS GUARANTEED AT 24 mA
· BALANCED PROPAGATION DELAYS:
    tPLH @ tPHL
· OPERATING VOLTAGE RANGE: VCC(OPR) = 2.0V to 3.6V (1.5V Data Retention)
· PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 373
· LATCH-UP PERFORMANCE EXCEEDS 500mA (JESD 17)
· ESD PERFORMANCE:
    HBM > 2000V (MIL STD 883 method 3015);
    MM > 200V


Pinout




Specifications

Symbol	Parameter	Value	Unit
VCC	DC Supply Voltage	0.5 to +7.0	V
VI	DC Input Voltage	0.5 VI +7.0	V
VO	DC Output Voltage	0.5 VO +7.0	V
VO	DC Output Voltage (High or Low State) (note 1)	0.5 VO VCC + 0.5	V
IIK	DC Input Diode Current	50	mA
IOK	DC Output Diode Current	50	mA
IO	DC Output Source/Sink Current	+50	mA
ICC	DC Supply Current Per Supply Pin	±100	mA
IGND	DC Ground Current Per Ground Pin	±100	mA
TSTG	Storage Temperature Range	65 to +150	°C

Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied
1) IO absolute maximum rating must be observed
2) VO < GND


Description

The 74LCX373M is a low voltage CMOS OCTAL D-TYPE LATCH with 3 STATE OUTPUT NON-INVERTING fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. It is ideal for low power and high speed 3.3V applications; it can be interfaced to 5V signal environment for both inputs and outputs. These 8 bit D-Type latch are controlled by a latch enable input (LE) and an output enable input (OE). While the LE inputs of the 74LCX373M is held at a high level, the Q outputs will follow the data input.

When the LE is taken low, the Q outputs of the 74LCX373M will be latched precisely at the logic level of D input data. While the (OE) input is low, the 8 outputs will be in a normal logic state (high or low logic level) and while (OE) is in high level, the outputs will be in a high impedance state. It has same speed performance at 3.3V than 5V AC/ACT family, combined with a lower power consumption. All inputs and outputs of the 74LCX373M are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.