74LCXZ16240

Features:

`5V tolerant inputs and outputs
`Guaranteed power up/down high impedance
`Supports live insertion/withdrawal
`2.7V3.6V V_CC specifications provided
`4.5 ns t<sub>PD</sub> max (V<sub>CC</sub> = 3.3V), 20 mA I<sub>CC</sub> max
` ±24 mA output drive (V_CC = 3.0V)
`Implements patented noise/EMI reduction circuitry
` Latch-up performance exceeds 500 mA
` ESD performance: Human body model > 2000V Machine model > 200V


Pinout




Specifications

Symbol	Parameter	Value	Conditions	Units
VCC	Supply Voltage	-0.5 to +7.0		V
VI	DC Input Voltage	-0.5 to +7.0		V
VO	DC Output Voltage	-0.5 to +7.0 -0.5 to VCC + 0.5	Output in 3-STATE or VCC = 01.5V Output in HIGH or LOW State (Note 2)	V
IIK	DC Input Diode Current	-50	VI < GND	mA
IOK	DC Output Diode Current	-50 +50	VO < GND VO > VCC	mA
IO	DC Output Source/Sink Current	±50		mA
ICC	DC Supply Current per Supply Pin	±100		mA
IGND	DC Ground Current per Ground Pin	±100		mA
TSTG	Storage Temperature	-65 to +150		°C

Description

The 74LCXZ16240 contains sixteen inverting buffers with 3-STATE outputs designed to be employed as a memory and address driver, clock driver, or bus-oriented transmitter/ receiver. The device is nibble controlled. Each nibble has separate 3-STATE control inputs which can be shorted together for full 16-bit operation.
When VCC is between 0 and 1.5V, the 74LCXZ16240 is in the high impedance state during power up or power down. This places the outputs in the high impedance (Z) state preventing intermittent low impedance loading or glitching in bus oriented applications.
The 74LCXZ16240 is designed for low voltage (2.7V or 3.3V) V_CC applications with capacity of interfacing to a 5V signal environment.
The 74LCXZ16240 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining CMOS low power dissipation.