74LVC841A

Features:

• 5-volt tolerant inputs/outputs, for interfacing with 5-volt logic
•Wide supply voltage range of 1.2 V to 3.6 V
• In accordance with the JEDEC standard no. 8-1 A
• Inputs accept voltages up to 5.5 V
• CMOS low power consumption
• Direct interface with TTL levels
• Flow-through pin-out architecture


Pinout




Specifications

SYMBOL PARAMETER CONDITIONS RATING UNIT
VCC   DC supply voltage 0.5 to +6.5 V
IIK DC input diode current VI  0 50 mA
VI DC input voltage Note 2 0.5 to +5.5 V
IOK DC output diode current VO VCC or VO  0
50 mA
VO DC output voltage Note 2 0.5 to VCC +0.5 V
IO DC output source or sink current VO = 0 to VCC
50 mA
IGND, ICC DC VCC or GND current
100 mA
Tstg Storage temperature range 65 to +150 °C
Power dissipation per package
PTOT plastic mini-pack (SO) above +70°C derate linearly with 8 mW/K 500
mW plastic shrink mini-pack (SSOP and TSSOP) above +60°C derate linearly with 5.5 mW/K 500
mW


Description

The 74LVC841A is a low-power, low-voltage, Si-gate CMOS device and superior to most advanced CMOS compatible TTL families. Inputs can be driven from either 3.3 V or 5 V devices. In 3-State operation, outputs can handle 5 V. This feature allows the use of these devices as translators in a mixed 3.3 V/5 V environment. The 74LVC841A is a 10-bit transparent latch featuring separate D-type inputs for each latch and 3-State outputs for bus oriented applications. A latch enable (LE) input and an output enable (OE) input are common to all internal latches. The 74LVC841A consists of ten transparent latches with 3-State true outputs. When LE is HIGH,data at the Dn inputs enters the latches. In this condition the latches are transparent, i.e., a latch output will change each time its corresponding D-input changes. When LE is LOW the latches store the information that was present at the D-inputs a set-up time preceding the HIGH-to-LOW transition of LE. When OE is LOW, the contents of the ten latches are available at the outputs.When OE of the 74LVC841A is HIGH, the outputs go to the high impedance OFF-state.Operation of the OE input does not affect the state of the latches.