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74LVTH16835

Features: Input and output interface capability to systems at 5V VCCBushold data inputs eliminate the need for external pull-up resistors to hold unused inputsLive insertion/extraction permittedPower Up/Down high impedance provides glitch-free bus loadingOutputs source/sink −32 mA/+64 mALatc...

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SeekIC No. : 004251564 Detail

74LVTH16835: Features: Input and output interface capability to systems at 5V VCCBushold data inputs eliminate the need for external pull-up resistors to hold unused inputsLive insertion/extraction permittedPowe...

74LVTH16835 Data Sheet

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Part Number:
74LVTH16835
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/4/29

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Product Details

Description



Features:

Input and output interface capability to systems at 5V VCC
Bushold data inputs eliminate the need for external pull-up resistors to hold unused inputs
Live insertion/extraction permitted
Power Up/Down high impedance provides glitch-free bus loading
Outputs source/sink −32 mA/+64 mA
Latch-up performance exceeds 500 mA


Pinout

Connection Diagram


Specifications

Symbol Parameter Value Conditions Units
VCC Supply Voltage −0.5 to +4.6   V
VI DC Input Voltage −0.5 to +7.0   V
VO DC Output Voltage −0.5 to +7.0
Output in 3-STATE
 V
−0.5 to +7.0 Output in HIGH or LOW State (Note 4)
IIK DC Input Diode Current −50 VI < GND mA
IOK DC Output Diode Current −50
VO < GND
 mA
IO DC Output Source/Sink Current 64 VO > VCC Output at HIGH State mA
128 VO > VCC Output at LOW State
ICC DC Supply Current per Supply Pin ±64   mA
IGND DC Ground Current per Ground Pin ±128   mA
TSTG Storage Temperature −65 to +150   °C



Description

The 74LVTH16835 consists of 18-bit universal bus drivers which combine D-type latches and D-type flip-flops to allow data flow in transparent, latched, or clocked modes. Data flow from A to Y is controlled by the output-enable (OE) input. This device operates in the transparent mode when the latch-enable (LE) input is HIGH. The A data is latched if the clock (CLK) input is held at a HIGH or LOW logic level. If LE is LOW, the A-bus data is stored in the latch/flip-flop on the LOW-to-HIGH transition of the CLK. When OE is HIGH, the outputs are in the high-impedance state.

The 74LVTH16835 data inputs include bushold, eliminating the need for external pull-up resistors to hold unused inputs.

The bus driver is designed for low voltage (3.3V) VCC applications, but with the capability to provide a TTL interface to a 5V environment. The 74LVTH16835 is fabricated with an advanced BiCMOS technology to achieve high speed operation similar to 5V ABT while maintaining low power dissipation.




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