74LVX112

Features: Input voltage level translation from 5V3VIdeal for low power/low noise 3.3V applicationsSpecificationsSupply Voltage (VCC) ...............................-0.5V to +7.0VDC Input Diode Current (IIK)VI-0.5V ..............................................................-20 mADC Input Voltage...

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SeekIC No. : 004251594 Detail

74LVX112: Features: Input voltage level translation from 5V3VIdeal for low power/low noise 3.3V applicationsSpecificationsSupply Voltage (VCC) ...............................-0.5V to +7.0VDC Input Diode Curre...

floor Price/Ceiling Price

Part Number:
74LVX112
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/4/29

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Product Details

Description



Features:

 Input voltage level translation from 5V3V
 Ideal for low power/low noise 3.3V applications



Specifications

Supply Voltage (VCC) ...............................-0.5V to +7.0V
DC Input Diode Current (IIK)
VI  -0.5V ..............................................................-20 mA
DC Input Voltage (VI)................................... -0.5V to 7V
DC Output Diode Current (IOK)
VO   -0.5V ...........................................................-20 mA
VO   VCC + 0.5V .................................................±20 mA
DC Output Voltage (VO)................. -0.5V to VCC + 0.5V
DC Output Source
or Sink Current (IO)............................................±25 mA
DC VCC or Ground Current
(ICC or IGND)..................................................... ±50 mA
Storage Temperature (TSTG) ................-65 to +150
Power Dissipation ............................................180 mW
 


Description

The 74LVX112 is a dual J-K Flip-Flop where each flip-flop has independent inputs (J, K, PRESET, CLEAR, and CLOCK) and outputs (Q, Q). These devices are edge sensitive and change states synchronously on the negative going transition of the clock pulse. Triggering occurs at a voltage level of the clock and is not directly related to the transition time. Clear and Preset are independent of the clock and are accomplished by a low logic level on the corresponding input. The J and K inputs can change when the clock is in either state without affecting the flip-flop, provided that they are in the desired state during the recommended setup and hold times relative to the falling edge of the clock.

The inputs tolerate voltages of the 74LVX112 up to 7V allowing the interface of 5V systems to 3V systems.




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