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82C900

Features: * Two interface channels are implemented for the communication with a host device: the Multiplexed Data/Address Bus can be used by an external CPU to read and write the TwinCAN's internal registers for initial configuration and control during normal operation. The standard Infineon Bus ...

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82C900: Features: * Two interface channels are implemented for the communication with a host device: the Multiplexed Data/Address Bus can be used by an external CPU to read and write the TwinCAN's internal...

82C900 Data Sheet

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Part Number:
82C900
Supply Ability:
5000

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Product Details

Description



Features:

* Two interface channels are implemented for the communication with a host device:
   the Multiplexed Data/Address Bus can be used by an external CPU to read and write the TwinCAN's internal registers for initial configuration and control during normal operation. The standard Infineon Bus Mode and the Motorola Bus Mode can be handled.
   alternatively, a Synchronous Serial Channel (SSC) may be selected to read out the initial TwinCAN's register configuration from a serial EEPROM. The SSC can be also used by an external control device (microcontroller, CPU, etc.) in order to exchange control and status information.
* Both communication channels are based on byte transfers. In order to minimize the communication overhead, all internal 16 bit and 32 bit wide registers can be accessed in Page Mode requiring only one address byte.
* Powerful initialization mechanism for all registers, the device can be configured via EEPROM, based on CAN messages or by an external host device.
* Additional input/output functionality controlled by CAN messages. The transmission of CAN messages can be triggered by input pins if the SSC is used for communication.
* The clock control unit can be supplied with an external clock. Alternatively, an on-chip oscillator may be used to generate a clock driving also an external device via an output pin.
* Power Saving features have been implemented. A Sleep Mode and a Power-Down Mode can be activated in order to minimize the power consumption. The clock control of the device can be controlled by CAN messages.
* The internal power saving status can be monitored at output pins. This allows flexible and powerful system partitioning.
* The Device Controller unit generates the internal target address by concatenating the contents of the PAGE register with the address delivered by the appropriate host read/write access.
* The Interrupt Control unit passes the interrupt requests generated by the TwinCAN controller to the external host via selectable output pins.
* The Port Control unit can be used to select the required functionality of the port pins operating as communication channel, CAN node function monitor, interrupt request line or general purpose I/O. Furthermore, the slew rate of pins configured for output operation can be adjusted via this module.


Pinout

Connection Diagram


Specifications

Parameter Symbol Limit Values Unit Notes
min. max.
Storage temperature TST -65 150  
Voltage on VDD pins withrespect to ground (VSS )
 VDD -0.5 6.5 V  
Voltage on any pin withrespect to ground (VSS )
 VIN -0.5 VDD +0.5 V  
Input current on any pin during overload condition   -10 10 mA  
Absolute sum of all input currents during overload condition     |100| mA  
Power dissipation PDISS   480 mW  

Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. During absolute maximum rating overload conditions (VIN >VDD  or VIN <V SS) thevoltage on VDD  pins with respect to ground (V SS) must not exceed the valuesdefined by the absolute maximum ratings.


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