83C196LD

Features:

22 MHz operation+
32 Kbytes of on-chip ROM (LC) 16 Kbytes of on-chip ROM (LD)
1 Kbyte of on-chip register RAM (LC) 384 bytes of on-chip register RAM (LD)
512 bytes of on-chip code RAM LC only)
Register-to-register architecture
Peripheral transaction server (PTS) with high-speed, microcoded interrupt service routines
Full-duplex serial I/O port with dedicated baud-rate generator
Enhanced full-duplex, synchronous  serial I/O port (SSIO)
High-speed event processor array
   -Six capture/compare channels
   -Two compare-only channels
   -Two 16-bit software timers
Programmable 8- or 16-bit external bus
Design enhancements for EMI  eduction
Oscillator failure detection circuitry
SFR register that indicates the source  of the last reset
Watchdog timer (WDT)
Cost reduced replacements for the 87C196JT and 87C196JR.
40 to +125 ambient temperature
52-pin PLCC package


Pinout




Specifications

Storage temperature ...............................  60 to +150
Supply voltage with respect to V_SS ..........0.5 V to +13.0 V
Power dissipation........................................................ 0.5 W


Description

The 83C196LC, 83C196LD are low-cost, pin-compatible replacements for the existing 87C196JT and 87C196JR, respectively. These products feature an enhanced synchronous serial I/O (SSIO) port for more flexible communication to other devices. The enhanced SSIO is compatible with Motorola's Serial Peripheral Interface (SPI) protocol and National's Microwire protocol. To optimize die size, the A/D converter was removed for use in those applications that use an off-chip A/D converter.

The MCS^(R)  96 microcontroller family members are all high-performance microcontrollers with 16-bit CPUs. The 83C196LC, 83C196LD are composed of a high-speed core with the following peripherals: an  asynchronous/synchronous serial I/O port (8096 compatible) with a dedicated 16-bit baud-rate generator; an
additional synchronous serial I/O port with full duplex master/slave transceivers; a flexible timer/counter structure with prescaler, cascading, and quadrature capabilities; six modularized, multiplexed high-speed I/O for capture and compare (called event processor array) with 200 ns resolution and double buffered inputs; and a sophisticated, prioritized interrupt structure with programmable peripheral transaction server (PTS). The 83C196LC has the highest memory density of the 52-pin MCS 96 microcontroller family, with 32 Kbytes of on-chip ROM, 1 Kbyte of on-chip register RAM, and 512 bytes of code RAM. The high memory integration
of the 83C196LC supports high functionality in a low pin-count package and the use of the C programming
language.