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MFG:ICS  Package Cooled:TSSOP-3.9-24P  D/C:6+  

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Part Number: 87004AGLF

 

MFG: ICS

Package Cooled: TSSOP-3.9-24P

D/C: 6+

Description: 4 LVCMOS OUT CLOCK GEN Features4 LVCMOS/LVTTL outputs, 7W typical output...


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87004AGLF General Description


4 LVCMOS OUT CLOCK GEN
Features
  • 4 LVCMOS/LVTTL outputs, 7W typical output impedance
  • Selectable CLK0, nCLK0 or CLK1, nCLK1 clock inputs
  • CLKx, nCLKx pairs can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
  • Internal bias on nCLK0 and nCLK1 to support
  • LVCMOS/LVTTL levels on CLK0 and CLK1 inputs
  • Output frequency range: 15.625MHz to 250MHz
  • Input frequency range: 15.625MHz to 250MHz
  • VCO range: 250MHz to 500MHz
  • External feedback for "zero delay" clock regeneration with configurable frequencies
  • Programmable dividers allow for the following output-to-input frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8
  • Fully integrated PLL
  • Cycle-to-cycle jitter: 45ps (maximum)
  • Output skew: 45ps (maximum)
  • Static phase offset: 50 ± 125ps (3.3V ± 5%)
  • Full 3.3V or 2.5V operating supply
  • 5V tolerant inputs
  • Available in both standard and lead-free RoHS complaint packages

Description
The ICS87004 is a highly versatile 1:4 Differential-to-LVCMOS/LVTTL Clock Generator and a member of the HiPerClockS? family of High Performance Clock Solutions from ICS. The ICS87004 has two selectable clock inputs. The CLK0, nCLK0 and CLK1, nCLK1 pairs can accept most standard differential input levels. Internal bias on the nCLK0 and nCLK1 inputs allows the CLK0 and CLK1 inputs to accept LVCMOS/LVTTL. The ICS87004 has a fully integrated PLL and can be configured as zero delay buffer, multiplier or divider and has an input and output frequency range of 15.625MHz to 250MHz. The reference divider, feedback divider and output divider are each programmable, thereby allowing for the following output-to-input frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8. The external feedback allows the device to achieve "zero delay" between the input clock and the output clocks. The PLL_SEL pin can be used to bypass the PLL for system test and debug purposes. In bypass mode, the reference clock is routed around the PLL and into the internal output dividers.

87004AGLF Maximum Ratings

Temperature C Voltage 3.3 V Package TSSOP 24 Speed NA Output Style Core Supply Voltage (VDD) No. of Outputs Min. Output Frequency Min. Input Frequency Output Supply Voltage (VDDO) No. of Inputs Input Style Max. Output Frequency Max. Input Frequency Temp. Grade Multiplication/Divide Value

87004AGLF datasheet

870
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