9P750CFLFT

Specifications Temperature C Voltage 3.3 V Package SSOP 48 Speed NA DescriptionPROGRAMMABLE DDR BUFRecommended Application of 9P750CFLFT:DDR Zero Delay Clock BufferProduct D...

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SeekIC No. : 004259639 Detail

9P750CFLFT: Specifications Temperature C Voltage 3.3 V Package SSOP 48 Speed NA Descr...

floor Price/Ceiling Price

Part Number:
9P750CFLFT
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/3/28

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Product Details

Description



Specifications

Temperature C Voltage 3.3 V Package SSOP 48 Speed NA


Description

PROGRAMMABLE DDR BUF
Recommended Application of 9P750CFLFT:DDR Zero Delay Clock BufferProduct Description/Features of 9P750CFLFT:? Low skew, low jitter PLL clock driver? 12 pairs of differential outputs support up toDDR400? Outputs divided into 3 groups- Group A is reference- Groups B and C have default offsets from GroupA, but also have skew programmable in stepsrelative to Group A.- Skew step (unit) set via RSTEP resistor? Static Phase Offset (SPO) of entire device can beprogrammed- RSPO sets overall SPO (analog delay)- I2C register settings allow fine tuning in stepsdefined by RSTEP? Spread spectrum tolerant inputs? 2.5 V differential reference clock inputSwitching Characteristics of 9P750CFLFT:? PEAK - PEAK jitter (>100MHz): <75ps? CYCLE - CYCLE jitter (>100MHz):<65ps? OUTPUT - OUTPUT skew: <50ps? DUTY CYCLE: 49% - 51%? Slew rate: 1V/ns - 2V/ns? Input clock duty cycle: 40% - 60%


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