9P750CGLF

Specifications

Temperature C Voltage 3.3 V Package TSSOP 48 Speed NA


Description

PROGRAMMABLE DDR BUF
Recommended Application:DDR Zero Delay Clock BufferProduct Description/Features of 9P750CGLF:? Low skew, low jitter PLL clock driver? 12 pairs of differential outputs support up toDDR400? Outputs divided into 3 groups- Group A is reference- Groups B and C have default offsets from GroupA, but also have skew programmable in stepsrelative to Group A.- Skew step (unit) set via RSTEP resistor? Static Phase Offset (SPO) of entire 9P750CGLF can beprogrammed- RSPO sets overall SPO (analog delay)- I2C register settings allow fine tuning in stepsdefined by RSTEP? Spread spectrum tolerant inputs? 2.5 V differential reference clock inputSwitching Characteristics of 9P750CGLF:? PEAK - PEAK jitter (>100MHz): <75ps? CYCLE - CYCLE jitter (>100MHz):<65ps? OUTPUT - OUTPUT skew: <50ps? DUTY CYCLE: 49% - 51%? Slew rate: 1V/ns - 2V/ns? Input clock duty cycle: 40% - 60%