A29L800

The A29L800 is an 8Mbit, 3.0 volt-only Flash memory  organized as 1,048,576 bytes of 8 bits or 524,288 words of  16 bits each. The 8 bits of data appear on I/O₀ - I/O₇; the 16  bits of data appear on I/O₀~I/O₁₅. The A29L800 is offered in
48-ball TFBGA,  44-pin SOP and 48-Pin TSOP packages.  This device is designed to be programmed in-system with the  standard system 3.0 volt V_CC supply. Additional 12.0 volt  V_PP is not required for in-system write or erase operations.
However, the A29L800 can also be programmed in standard  EPROM programmers. 

The A29L800 has the first toggle bit, I/O6, which indicates  whether an Embedded Program or Erase is in progress, or it  is in the Erase Suspend. Besides the I/O₆  toggle bit, the  A29L800 has a second toggle bit, I/O₂, to indicate whether  the addressed sector is being selected for erase. The  A29L800 also offers the ability to program in the Erase  Suspend mode. The standard A29L800 offers access times  of 70 and 90ns, allowing high-speed microprocessors to  operate without wait states. To eliminate bus contention the  device has separate chip enable  (CE ), write enable  (WE )  and output enable (OE ) controls.

The device requires only a single 3.0 volt power supply for  both read and write functions. Internally generated and  regulated voltages are provided for the  program and erase  operations. 

The A29L800 is entirely software command set compatible  with the JEDEC single-power-supply Flash standard.  Commands are written to the command register using  standard microprocessor write timings. Register contents serve as  input to an internal state-machine that controls the  erase and programming circuitry. Write cycles also internally  latch addresses and data needed for the programming and  erase operations. Reading data out of the device is similar to
reading from other Flash or EPROM devices. 

Device programming occurs by writing the proper program  command sequence. This initiates the Embedded Program  algorithm - an internal algorithm that automatically times the  program pulse widths and verifies proper program margin. 

Device erasure occurs by executing the proper erase  command sequence. This initiates the Embedded Erase  algorithm  - an internal algorithm that automatically
preprograms the array (if it is not already programmed)  before executing the erase operation. During erase, the  device automatically times the erase pulse widths and  verifies proper erase margin. The Unlock Bypass mode  facilitates faster programming times by requiring only two  write cycles to program data instead of four.

The host system can detect whether  a program or erase  operation is complete by observing the RY / BY pin, or  by  reading the I/O₇ (Data  Polling) and I/O₆ (toggle) status bits.  After a program or erase cycle has been completed, the  device is ready to read array data or accept another  command. 

The sector erase architecture allows memory sectors to be  erased and reprogrammed without affecting the data  contents of other sectors. The A29L800 is fully erased when  shipped from the factory. 

The hardware sector protection feature disables operations  for both program and erase in any combination of the  sectors of memory. This can be achieved via programming  equipment. 

The Erase Suspend/Erase Resume feature enables the user  to put erase on hold for any period of time to read data from,  or program data to, any other sector that is not selected for  erasure. True background erase can thus be achieved. 

The hardware  RESET  pin terminates any operation in  progress and resets the internal state machine to reading  array data. The RESET pin may be tied to the system reset  circuitry. A system reset would thus also reset the device,  enabling the system microprocessor to read the boot-up  firmware from the Flash memory.

The device offers two power-saving features. When  addresses have been stable for a specified amount of time,  the device enters the automatic sleep mode. The system can  also place the device into the standby mode. Power  consumption is greatly reduced in both these modes.