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Part Number: A54SX32P-3BG208I
Description: Actel's SX family of FPGAs features a sea-of-modules architecture that delivers device performance and integration leve...
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A54SX32P-3BG208I
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General Description
A54SX32P-3BG208I General Description
Actel's SX family of FPGAs features a sea-of-modules architecture that delivers device performance and integration levels not currently achieved by any other FPGA architecture. SX devices greatly simplify design time, enable dramatic reductions in design costs and power consumption, and further decrease time to market for performance-intensive applications.
Actel's SX architecture features two types of logic modules, the combinatorial cell (C-cell) and the register cell (R-cell), each optimized for fast and efficient mapping of synthesized logic functions. The routing and interconnect resources are in the metal layers above the logic modules, providing optimal use of silicon. This enables the entire floor of the device to be spanned with an uninterrupted grid of fine-grained, synthesis-friendly logic modules (or "sea-of-modules"), which reduces the distance signals have to travel between logic modules. To minimize signal propagation delay, SX devices employ both local and general routing resources. The high-speed local routing resources (DirectConnect and FastConnect) enable very fast local signal propagation that is optimal for fast counters, state machines, and datapath logic. The general system of segmented routing tracks allows any logic module in the array to be connected to any other logic or I/O module. Within this system, propagation delay is minimized by limiting the number of antifuse interconnect elements to five (90 percent of connections typically use only three antifuses). The unique local and general routing structure featured in SX devices gives fast and predictable performance, allows 100 percent pin-locking with full logic utilization, enables concurrent PCB development, reduces design time, and allows designers to achieve performance goals with minimum effort.
Further complementing SX's flexible routing structure is a hard-wired, constantly loaded clock network that has been tuned to provide fast clock propagation with minimal clock skew. Additionally, the high performance of the internal logic has eliminated the need to embed latches or flip-flops in the I/O cells to achieve fast clock-to-out or fast input set-up times. SX devices have easy-to-use I/O cells that do not require HDL instantiation, facilitating design re-use and reducing design and verification time.
A54SX32P-3BG208I Maximum Ratings
| Symbol | Parameter | Limits | Units |
| VCCR2 | DC Supply Voltage3 | 0.3 to +6.0 | V |
| VCCA2 | DC Supply Voltage | 0.3 to +4.0 | V |
| VCCI2 | DC Supply Voltage (A54SX08, A54SX16, A54SX32) |
0.3 to +4.0 | V |
| VCCI2 | DC Supply Voltage (A54SX16P) |
0.3 to +6.0 | V |
| VI | Input Voltage | 0.5 to +5.5 | V |
| VO | Output Voltage | 0.5 to +3.6 | V |
| IIO | I/O Source Sink Current3 |
30 to +5.0 | mA |
| TSTG | Storage Temperature | 65 to +150 |
A54SX32P-3BG208I Features
• 66 MHz PCI
• CPLD and FPGA Integration
• Single Chip Solution
• 100% Resource Utilization with 100% Pin Locking
• 3.3V Operation with 5.0V Input Tolerance
• Very Low Power Consumption
• Deterministic, User-Controllable Timing
• Unique In-System Diagnostic and Debug capability with Silicon Explorer II
• Boundary Scan Testing in Compliance with IEEE Standard 1149.1 (JTAG)
• Secure Programming Technology Prevents Reverse Engineering and Design Theft
• CPLD and FPGA Integration
• Single Chip Solution
• 100% Resource Utilization with 100% Pin Locking
• 3.3V Operation with 5.0V Input Tolerance
• Very Low Power Consumption
• Deterministic, User-Controllable Timing
• Unique In-System Diagnostic and Debug capability with Silicon Explorer II
• Boundary Scan Testing in Compliance with IEEE Standard 1149.1 (JTAG)
• Secure Programming Technology Prevents Reverse Engineering and Design Theft
A54SX32P-3BG208I
PDF/DataSheet Download
- Datasheet: A54SX32P-3BG208I
- File Size: 425875 KB
- Manufacturer: ETC [ETC]
- Click here to Download
- ·A540
- POWEREX [Powerex Power Semiconductors]
- SILICON RECTIFIER
- 121617 KB
- ·A540L
- POWEREX [Powerex Power Semiconductors]
- SILICON RECTIFIER
- 121617 KB
- ·A540LA
- POWEREX [Powerex Power Semiconductors]
- SILICON RECTIFIER
- 121617 KB
- ·A540LB
- POWEREX [Powerex Power Semiconductors]
- SILICON RECTIFIER
- 121617 KB
- ·A540LC
- POWEREX [Powerex Power Semiconductors]
- SILICON RECTIFIER
- 121617 KB
- ·A540LD
- POWEREX [Powerex Power Semiconductors]
- SILICON RECTIFIER
- 121617 KB
- ·A54SX08
- ETC [ETC]
- 54SX Family FPGAs
- 425875 KB
- ·A54SX08-1BG208
- ETC [ETC]
- 54SX Family FPGAs
- 425875 KB
A54SX32P-3BG208I Relative Products
A54SX32A-3BG208
A54SX32A
The HiRel versions of Actel SX-A family FPGAs offer advantages for commercial applications and all types of military and high reliability equipment. The HiRel versions are fully pin compatible, allowing designs to migrate across different applications that d...
A54SX32
Actel's RadTolerant (RT) and HiRel versions of the SX Family of FPGAs offer all of these advantages for applications such as commercial and military satellites, deep space probes, and all types of military and high reliability equipment.The RT and HiRel vers...
A54SX16P
Actel's SX family of FPGAs features a sea-of-modules architecture that delivers device performance and integration levels not currently achieved by any other FPGA architecture. SX devices greatly simplify design time, enable dramatic reductions in design cos...
A54SX16A-TQ144-M134
The A54SX16A-TQ144-M134 is one member of the A54SX16A-TQ144 family which is designed as the SX-A Family FPGA. It has four points of specifications:(1)12,000 to 108,000 available system gates; (2)up to 360 user-programmable I/O pins; (3)up to 2,012 dedicated ...
A54SX16-2
The Arbiter core A54SX16-2is used to efficiently manage access to a PCI bus that is shared by several masters. Access to the PCI bus is automatically determined by the individual priorities of each master.In the most common application, customers use an embe...
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