AD1877*

The AD1877 is a stereo, 16-bit oversampling ADC based on Sigma Delta () technology intended primarily for digital audio bandwidth applications requiring a single 5 V power supply. Each single-ended channel consists of a fourth-order one-bit noise shaping modulator and a digital decimation filter. An onchip voltage reference, stable over temperature and time, defines the full-scale range for both channels. Digital output data from both channels are time-multiplexed to a single, flexible serial interface. The AD1877 accepts a 256 * F_S or a 384 * F_S input clock (F_S is the sampling frequency) and operates in both serial port "master" and "slave" modes. In slave mode, all clocks must be externally derived from a common source.

Input signals are sampled at 64 * F_S onto internally buffered switched-capacitors, eliminating external sample-and-hold amplifiers and minimizing the requirements for antialias filtering at the input. With simplified antialiasing, linear phase can be preserved across the passband. The on-chip single-ended to differential signal converters save the board designer from having to provide them externally. The AD1877's internal differential architecture provides increased dynamic range and excellent power supply rejection characteristics. The AD1877's proprietary fourth-order differential switched-capacitor modulator architecture shapes theone-bit comparator's quantization noise out of the audio passband. The high order of the modulator randomizes the modulator output, reducing idle tones in the AD1877 to very low levels.Because its modulator is single-bit, AD1877 is inherently monotonic and has no mechanism for producing differential linearity errors.

The input section of the AD1877 uses autocalibration to correct any dc offset voltage present in the circuit, provided that the inputs are ac coupled. The single-ended dc input voltage can swing between 0.7 V and 3.8 V typically. The AD1877 antialias input circuit requires four external 470 pF NPO ceramic chip filter capacitors, two for each channel. No active electronics are needed. Decoupling capacitors for the supply and reference pins are also required.

The dual digital decimation filters are triple-stage, finite impulse response filters for effectively removing the modulator's high frequency quantization noise and reducing the 64 * F_S single-bit output data rate to an F_S word rate. They provide linear phase and a narrow transition band that properly digitizes 20 kHz signals at a 44.1 kHz sampling frequency. Passband ripple is less than 0.006 dB, and stopband attenuation exceeds 90 dB.