AD805

      The AD805 has the following features including 155 Mbps Clock Recovery and Data Retiming;Permits CCITT G.958 Type A Jitter Tolerance;Permits CCITT G.958 Type B Jitter Transfer;Random Jitter: 0.68 rms;Pattern Jitter: Virtually Eliminated;Jitter Peaking: Fundamentally None;Acquisition: 30 Bit Periods;Accepts NRZ Data without Preamble;Single Supply Operation: 5.2 V or +5 V;10 KH ECL Compatible.
      The AD805 is intended to operate with standard ECL signal levels at the data input. Although not recommended, smaller input signals are tolerable. Figure 6 shows the bit error rate performance versus input signal-to-noise ratio for input signal amplitudes of full 900 mV ECL, and decreased amplitudes of 80 mV and 20 mV. Wideband amplitude noise is summed with the data signals as shown in Figure 2. The full ECL, 80 mV, and 20 mV input signals give virtually indistinguishable results.
      Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of the specification is not implied. Exposure to an absolute maximum rating condition for an extended period may adversely affect devic reliablity.This is the operating temperature range of the AD805 in the circuit. Each of the additional components of the circuit is held at 25°C, nominal. The operating temperature range of the circuit can be extended to the operating temperature range of the AD805 through the selection of circuit components that operate from TMIN to TMAX.
      The AD805 is a delay- and phase- locked loop circuit for clock recovery and data retiming from an NRZ-encoded data stream. Figure 8 is a block diagram of the device shown with an external VCXO. The AD805-VCXO circuit tracks the phase of the input data using two feedback loops that share a common control voltage. A high speed delay-locked loop path uses an on-chip voltage-controlled phase shifter (VCPS) to track the high frequency components of jitter on the input data. A separate frequency control loop, using the external VCXO, tracks the low frequency components of jitter on the input data.