AD9430 General Description
AD9430 Maximum Ratings
AVDD, DRVDD.. .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 V
Analog Inputs . . . . . . . . . . .. . .. .0.5 V to AVDD + 0.5 V
Digital Inputs . . .. . . . . . . . .. . . .0.5 V to DRVDD + 0.5 V
REFIN Inputs . . . . . . . . . . . . . . . 0.5 V to AVDD + 0.5 V
Digital Output Current . . . . . . . . . . . . . . . . . . . . . . 20 mA
Operating Temperature . . . . . . . . . . ... . 55 to +125
Storage Temperature . . . . . . . . . . . . . ...65 to +150
Maximum Junction Temperature . . . . . . . . . . . . . . . 150
Maximum Case Temperature . . . . . . . . . . . . . . . . . . 150
JA2 . . . . . . .. . . . . . . . . . . . . . . . . . . . . .25/W, 32/W
AD9430 Features
SNR = 65dB @ Fin up to 65MHz at 170Msps
ENOB of 10.3 @ Fin up to 65MHz at 170 Msps (-1dBFs)
SFDR = -80dBc @ Fin up to 65MHz at 170Msps (-1dBFs)
Excellent Linearity:
- DNL = +/- 1 lsb (typ)
- INL = +/- 1.5 lsb (typ)
Two Output Data options
- Demultiplexed 3.3V CMOS outputs each at 85 Msps
- LVDS at 170Msps
700 MHz Full Power Analog Bandwidth
Onchip reference and track/hold
Power dissipation = 1.25W typical at 170Msps
1.5V Input voltage range
+3.3V Supply Operation
Output data format option
Data Sync input and Data Clock output provided
Interleaved or parallel data output option (CMOS)
Clock Duty Cycle Stabilizer.
AD9430 Typical Application
Wireless and Wired Broadband Communications
- Wideband carrier frequency systems
- Cable Reverse Path
Communications Test Equipment
Radar and Satellite sub-systems
Power Amplifier Linearization
AD9430 Connection Diagram
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