AD9430 Selling Leads, Price trend, AD9430 DataSheet download, circuit diagram from SeekIC.com

Features: SNR = 65dB @ Fin up to 65MHz at 170Msps ENOB of 10.3 @ Fin up to 65MHz at 170 Msps (-1dBFs) SFDR = -80dBc @ Fin up to 65MHz at 170Msps (-1dBFs) Excellent Linearity: - DNL = +/- 1 lsb (typ) - INL = +/- 1.5 lsb (typ) Two Output Data options - Demultiplexed 3.3V CMOS outputs each at 85 Msps...

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SeekIC No. : 004273080 Detail

AD9430: Features: SNR = 65dB @ Fin up to 65MHz at 170Msps ENOB of 10.3 @ Fin up to 65MHz at 170 Msps (-1dBFs) SFDR = -80dBc @ Fin up to 65MHz at 170Msps (-1dBFs) Excellent Linearity: - DNL = +/- 1 lsb (typ)...

AD9430 Data Sheet

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Part Number:: AD9430
Supply Ability:: 5000

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Upload time: 2024/4/30

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Product Details

Description

Features:

SNR = 65dB @ Fin up to 65MHz at 170Msps
ENOB of 10.3 @ Fin up to 65MHz at 170 Msps (-1dBFs)
SFDR = -80dBc @ Fin up to 65MHz at 170Msps (-1dBFs)
Excellent Linearity:
- DNL = +/- 1 lsb (typ)
- INL = +/- 1.5 lsb (typ)
Two Output Data options
- Demultiplexed 3.3V CMOS outputs each at 85 Msps
- LVDS at 170Msps
700 MHz Full Power Analog Bandwidth
Onchip reference and track/hold
Power dissipation = 1.25W typical at 170Msps
1.5V Input voltage range
+3.3V Supply Operation
Output data format option
Data Sync input and Data Clock output provided
Interleaved or parallel data output option (CMOS)
Clock Duty Cycle Stabilizer.

Application

Wireless and Wired Broadband Communications
- Wideband carrier frequency systems
- Cable Reverse Path
Communications Test Equipment
Radar and Satellite sub-systems
Power Amplifier Linearization

Pinout

Connection Diagram

Specifications

Resolution (Bits)	12bit
T-Put Rate	210000000SPS
# Chan	1
Supply V	Single(+3.3)
Pwr Diss	1.7W

Interface	LVDS,Par
Ain Range	1.5 V p-p
SNR (dB)	65dB
Pkg Type	QFP

AVDD, DRVDD.. .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 V
Analog Inputs . . . . . . . . . . .. . .. .0.5 V to AVDD + 0.5 V
Digital Inputs . . .. . . . . . . . .. . . .0.5 V to DRVDD + 0.5 V
REFIN Inputs . . . . . . . . . . . . . . . 0.5 V to AVDD + 0.5 V
Digital Output Current . . . . . . . . . . . . . . . . . . . . . . 20 mA
Operating Temperature . . . . . . . . . . ... . 55 to +125
Storage Temperature . . . . . . . . . . . . . ...65 to +150
Maximum Junction Temperature . . . . . . . . . . . . . . . 150
Maximum Case Temperature . . . . . . . . . . . . . . . . . . 150
JA² . . . . . . .. . . . . . . . . . . . . . . . . . . . . .25/W, 32/W

Description

The AD9430 is a 12-bit monolithic sampling analog-to-digital converter optimized for high performance, low power, and ease of use. The product operates up to a 210 MSPS conversion rate and is

The AD9430 is a 12-bit monolithic sampling analogtodigital converter with an onchip trackandhold circuit and is optimized for low cost, low power, small size and ease of use. The product operates up to 170 Msps conversion rate and is optimized for outstanding dynamic performance in wideband carrier systems.

The ADC AD9430 requires a +3.3V power supply and a differential encode clock for full performance operation. No external reference or driver components are required for many applications. The digital outputs are TTL/CMOS or LVDS compatible. Separate output power supply pins support interfacing with 3.3V CMOS logic.

An output data format select option of two's complement or offset binary is supported. In CMOS mode two output buses support demultiplexed data up to 85 Msps rates. A data sync input is supported for proper output data port alignment and a data clock output is available for proper output data timing. Fabricated on an advanced BiCMOS process, the AD9430 is
available in a 100 pin surface mount plastic package (100 TQFP ePAD) specified over the industrial temperature range(40°C to +85°C).

AD9430

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