AD9773

12 bit Resolution, 160 MSPS Conversion Rate Selectable 2×/4×/8× Interpolating Filter Programmable Channel Gain and Offset Adjustment Fs/2,4,8 Digital Quadrature Modulation Capability
Direct IF Transmission Mode for 70MHz+ IFs Enables Image Rejection Architecture Fully Compatible SPI Port Excellent AC Performance SFDR -69dBc @ 2-35MHz WCDMA ACPR -70dB @ IF=16.25 MHz Internal PLL Clock Multiplier Selectable Internal Clock Divider Versatile Clock Input Differential/Single Ended Sine Wave or TTL/CMOS/LVPECL Compatibl Versatile Input Data Interface 2,s Complement/Straight Binary Data Coding Dual Port or Single Port Interleaved Data Single +3.3V Supply Operation Power Dissipation: <700 mW @ 3.3V On-chip 1.2 V Reference, 80-Lead LQFP