AD9833

This low power DDS device is a numerically controlled oscillator employing a phase accumulator, a SIN ROM and a 10-bit D/A converter integrated on a single CMOS chip. Clock rates up to 25 MHz are supported with a power supply from +2.3 V to +5.5 V.

Capability for phase modulation and frequency modula-tion is provided. Frequency accuracy can be controlled to one part in 0.25 billion. Modulation is effected by loading registers through the serial interface.

The AD9833 offers a variety of output waveforms from the VOUT pin. The SIN ROM can be bypassed so that a linear up/down ramp is output from the DAC.  If the SIN ROM is not by-passed, a sinusoidal output is available.Also, if a clock output is required, the MSB of the DAC data can be output.

The digital section is internally operated at +2.5 V, irre-spective of the value of VDD, by an on board regulator which steps down VDD to +2.5 V, when VDD exceeds+2.5 V.

The AD9833 has a power-down function (SLEEP). This allows sections of the device which are not being used to be powered down, thus minimising the current consump-tion of the part e.g the DAC can be powered down when a clock output is being generated. The AD9833 is available in a 10-pin  SOIC package.