Features: 205 MSPS Maximum Conversion Rate
500 MHz Programmable Analog Bandwidth
0.5 V to 1.0 V Analog Input Range
Less than 450 ps p-p PLL Clock Jitter @ 205 MSPS
3.3 V Power Supply
Full Sync Processing
Sync Detect for "Hot Plugging"
2:1 Analog Input Mux
4:2:2 Output Format Mode
Midscale Clamping
Power-Down Mode
Low Power: <1 W Typical @ 205 MSPSApplicationRGB Graphics Processing
LCD Monitors and Projectors
Plasma Display Panels
Scan Converters
Microdisplays
Digital TVPinout
SpecificationsVD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6 V
VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6 V
Analog Inputs . . . . . . . . . . . . . . . . . . . . . . . . VD to 0.0 V
VREF IN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VD to 0.0 V
Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . 5 V to 0.0 V
Digital Output Current . . . . . . . . . . . . . . . . . . . . . .20 mA
Operating Temperature . . . . . . . . . . . 25°C to +85°C
Storage Temperature . . . . . . . . . . . . 65°C to +150°C
Maximum Junction Temperature . . . . . . . . . . . . . .150°C
Maximum Case Temperature . . . . . . . . . . . . . . . . 150°CDescriptionThe AD9888 is a complete 8-bit, 205 MSPS monolithic analog interface optimized for capturing RGB graphics signals from personal computers and workstations. Its 205 MSPS encode rate capability and full-power analog bandwidth of 500 MHz supports resolutions up to UXGA (1600 * 1200 at 75 Hz). For ease of design and to minimize cost, the AD9888 is a fully integrated interface solution for flat panel displays.
The AD9888 includes an analog interface with a 205 MHz triple ADC with internal 1.25 V reference, PLL to generate a pixel clock from HSYNC and COAST, midscale clamping, and programmable gain, offset, and clamp control. The user provides only a 3.3 V power supply, analog input, and HSYNC and COAST signals. Three-state CMOS outputs may be powered from 2.5 V to 3.3V.
The AD9888's on-chip PLL generates a pixel clock from HSYNC and COAST inputs. Pixel clock output frequencies range from 10MHz to 205 MHz. PLL clock jitter is less than 450 ps p-p
typical at 205 MSPS. When the COAST signal is presented, the PLL maintains its output frequency in the absence of HSYNC.A sampling phase adjustment is provided. Data, HSYNC, and Clock output phase relationships are maintained. The PLL can be disabled and an external clock input provided as the pixel clock. The AD9888 also offers full sync processing for compos-
ite sync and Sync-on-Green applications.
A clamp signal is generated internally or may be provided by the user through the CLAMP input pin. This interface is fully pro- grammable via a 2-wire serial interface. Fabricated in an advanced CMOS process, the AD9888 is pro-vided in a space-saving 128-lead MQFP surface mount plastic package and is specified over the 0°C to 70°C temperature range.
AD9888 Data Sheet
