Features: New AD9949A supports CCD line length > 4096 pixels Correlated double sampler (CDS) 0 dB to 18 dB pixel gain amplifier (PxGA®) 6 dB to 42 dB 10-bit variable gain amplifier (VGA) 12-bit, 36 MSPS analog-to-digital converter (ADC) Black level clamp with variable level control Complete...
AD9949: Features: New AD9949A supports CCD line length > 4096 pixels Correlated double sampler (CDS) 0 dB to 18 dB pixel gain amplifier (PxGA®) 6 dB to 42 dB 10-bit variable gain amplifier (VGA) 12-b...
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Parameter |
Min Typ Max |
Unit |
TEMPERATURE RANGE Operating Storage |
−20 +85 −65 +150 |
°C °C |
MAXIMUM CLOCK RATE |
36 |
MHz |
POWER SUPPLY VOLTAGE AVDD, TCVDD (AFE, Timing Core) HVDD (H1 to H4 Drivers) RGVDD (RG Driver) DRVDD (D0 to D11 Drivers) DRVDD (D0 to D11 Drivers) |
2.7 3.0 3.6 2.7 3.0 3.6 2.7 3.0 3.6 2.7 3.0 3.6 2.7 3.0 3.6 |
V V V V V |
POWER DISSIPATION 36 MHz, HVDD = RGVDD = 3 V, 100 pF H1 to H4 Loading1 Total Shutdown Mode |
320 1 |
mW mW |
Resolution (Bits) | 12bit |
Input Range (V p-p) | 1V p-p |
Sample Rate (MSPS) | 36MSPS |
Power Dissipation (mW) | 320mW |
DNL typ (LSB) | ±0.5LSB |
PGA Range (dB) | 0 to 36 |
The AD9949 is a highly integrated CCD signal processor for digital still camera applications. Specified at pixel rates of up to 36 MHz, the AD9949 consists of a complete analog front end with A/D conversion, combined with a programmable timing driver. The Precision Timing core allows adjustment of high speed clocks with < 600 ps resolution.
The analog front end includes black level clamping, CDS, PxGA, VGA, and a 36 MSPS, 12-bit ADC. The timing driver provides the high speed CCD clock drivers for RG and H1 to H4. Operation is programmed using a 3-wire serial interface.
Packaged in a space-saving, 40-lead LFCSP package, the AD9949 is specified over an operating temperature range of −20°C to +85°C.